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[PowerPC] Add clang options to control MMA support 

This patch adds frontend and backend options to enable and disable
the PowerPC MMA operations added in ISA 3.1. Instructions using these
options will be added in subsequent patches.

Differential Revision: https://reviews.llvm.org/D81442
This commit is contained in:
Baptiste Saleil 2020-08-24 09:14:16 -05:00
parent 235f9f7fe9
commit 512e256c0d
11 changed files with 45 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
clang/include/clang/Driver/Options.td
View File

@ -2506,6 +2506,8 @@ def mlongcall: Flag<["-"], "mlongcall">,
Group<m_ppc_Features_Group>;
def mno_longcall : Flag<["-"], "mno-longcall">,
Group<m_ppc_Features_Group>;
def mmma: Flag<["-"], "mmma">, Group<m_ppc_Features_Group>;
def mno_mma: Flag<["-"], "mno-mma">, Group<m_ppc_Features_Group>;
def maix_struct_return : Flag<["-"], "maix-struct-return">,
Group<m_Group>, Flags<[CC1Option]>,
HelpText<"Return all structs in memory (PPC32 only)">;

18
clang/lib/Basic/Targets/PPC.cpp
View File

@ -64,6 +64,8 @@ bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
FloatABI = SoftFloat;
} else if (Feature == "+paired-vector-memops") {
PairedVectorMemops = true;
} else if (Feature == "+mma") {
HasMMA = true;
}
// TODO: Finish this list and add an assert that we've handled them
// all.
@ -184,6 +186,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__FLOAT128__");
if (HasP9Vector)
Builder.defineMacro("__POWER9_VECTOR__");
if (HasMMA)
Builder.defineMacro("__MMA__");
if (HasP10Vector)
Builder.defineMacro("__POWER10_VECTOR__");
@ -221,6 +225,7 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
// - float128
// - power9-vector
// - paired-vector-memops
// - mma
// - power10-vector
// then go ahead and error since the customer has expressed an incompatible
// set of options.
@ -244,6 +249,7 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
Found |= FindVSXSubfeature("+float128", "-mfloat128");
Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector");
Found |= FindVSXSubfeature("+paired-vector-memops", "-mpaired-vector-memops");
Found |= FindVSXSubfeature("+mma", "-mmma");
Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector");
// Return false if any vsx subfeatures was found.
@ -345,6 +351,7 @@ void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap<bool> &Features) const {
Features["htm"] = false; // HTM was removed for P10.
Features["paired-vector-memops"] = true;
Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
return;
@ -373,6 +380,7 @@ bool PPCTargetInfo::hasFeature(StringRef Feature) const {
.Case("power10-vector", HasP10Vector)
.Case("pcrelative-memops", HasPCRelativeMemops)
.Case("spe", HasSPE)
.Case("mma", HasMMA)
.Default(false);
}
@ -389,6 +397,7 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
.Case("paired-vector-memops", true)
.Case("power10-vector", true)
.Case("float128", true)
.Case("mma", true)
.Default(false);
if (FeatureHasVSX)
Features["vsx"] = Features["altivec"] = true;
@ -406,13 +415,14 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
if ((Name == "altivec") || (Name == "vsx"))
Features["vsx"] = Features["direct-move"] = Features["power8-vector"] =
Features["float128"] = Features["power9-vector"] =
Features["paired-vector-memops"] = Features["power10-vector"] =
false;
Features["paired-vector-memops"] = Features["mma"] =
Features["power10-vector"] = false;
if (Name == "power8-vector")
Features["power9-vector"] = Features["paired-vector-memops"] =
Features["power10-vector"] = false;
Features["mma"] = Features["power10-vector"] = false;
else if (Name == "power9-vector")
Features["paired-vector-memops"] = Features["power10-vector"] = false;
Features["paired-vector-memops"] = Features["mma"] =
Features["power10-vector"] = false;
if (Name == "pcrel")
Features["pcrelative-memops"] = false;
else

1
clang/lib/Basic/Targets/PPC.h
View File

@ -58,6 +58,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
// Target cpu features.
bool HasAltivec = false;
bool HasMMA = false;
bool HasVSX = false;
bool HasP8Vector = false;
bool HasP8Crypto = false;

9
clang/test/Driver/ppc-dependent-options.cpp
View File

@ -58,6 +58,14 @@
// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpaired-vector-memops %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-PAIRED-VEC-MEMOPS
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mmma %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=future -std=c++11 -mno-vsx -mmma %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA
// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \
// RUN: -mcpu=power9 -std=c++11 -mno-vsx -mfloat128 -mpower9-vector %s 2>&1 | \
// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MULTI
@ -103,5 +111,6 @@ static_assert(false, "Neither enabled");
// CHECK-NVSX-PAIRED-VEC-MEMOPS: error: option '-mpaired-vector-memops' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx'
// CHECK-NVSX-MMA: error: option '-mmma' cannot be specified with '-mno-vsx'
// CHECK-NVSX: Neither enabled
// CHECK-VSX: VSX enabled

5
clang/test/Preprocessor/init-ppc64.c
View File

@ -628,6 +628,7 @@
// PPCPOWER10:#define _ARCH_PWR7 1
// PPCPOWER10:#define _ARCH_PWR8 1
// PPCPOWER10:#define _ARCH_PWR9 1
// PPCPOWER10:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
//
@ -645,6 +646,10 @@
// PPCFUTURE:#define _ARCH_PWR8 1
// PPCFUTURE:#define _ARCH_PWR9 1
// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
// PPCFUTURE:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s
// PPC-MMA:#define __MMA__ 1
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
// PPC-FLOAT128:#define __FLOAT128__ 1

7
llvm/lib/Target/PowerPC/PPC.td
View File

@ -238,6 +238,10 @@ def FeaturePairedVectorMemops:
SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
"32Byte load and store instructions",
[FeatureISA3_0]>;
def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
"Enable MMA instructions",
[FeatureP8Vector, FeatureP9Altivec,
FeaturePairedVectorMemops]>;
def FeaturePredictableSelectIsExpensive :
SubtargetFeature<"predictable-select-expensive",
@ -343,7 +347,8 @@ def ProcessorFeatures {
// still exist with the exception of those we know are Power9 specific.
list<SubtargetFeature> P10AdditionalFeatures =
[DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs,
FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops];
FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA,
FeaturePairedVectorMemops];
list<SubtargetFeature> P10SpecificFeatures = [];
list<SubtargetFeature> P10InheritableFeatures =
!listconcat(P9InheritableFeatures, P10AdditionalFeatures);

1
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -504,6 +504,7 @@ multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">;
def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">;
def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">;
def MMA : Predicate<"PPCSubTarget->hasMMA()">;
let Predicates = [PrefixInstrs] in {
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {

4
llvm/lib/Target/PowerPC/PPCScheduleP9.td
View File

@ -41,9 +41,9 @@ def P9Model : SchedMachineModel {
let CompleteModel = 1;
// Do not support SPE (Signal Processing Engine), prefixed instructions on
// Power 9, paired vector mem ops, PC relative mem ops, or instructions
// Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
// introduced in ISA 3.1.
let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops,
let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
PCRelativeMemops, IsISA3_1];
}

1
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
View File

@ -73,6 +73,7 @@ void PPCSubtarget::initializeEnvironment() {
HasP8Crypto = false;
HasP9Vector = false;
HasP9Altivec = false;
HasMMA = false;
HasP10Vector = false;
HasPrefixInstrs = false;
HasPCRelativeMemops = false;

2
llvm/lib/Target/PowerPC/PPCSubtarget.h
View File

@ -107,6 +107,7 @@ protected:
bool HasP10Vector;
bool HasPrefixInstrs;
bool HasPCRelativeMemops;
bool HasMMA;
bool HasFCPSGN;
bool HasFSQRT;
bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
@ -260,6 +261,7 @@ public:
bool hasP10Vector() const { return HasP10Vector; }
bool hasPrefixInstrs() const { return HasPrefixInstrs; }
bool hasPCRelativeMemops() const { return HasPCRelativeMemops; }
bool hasMMA() const { return HasMMA; }
bool pairedVectorMemops() const { return PairedVectorMemops; }
bool hasMFOCRF() const { return HasMFOCRF; }
bool hasISEL() const { return HasISEL; }

4
llvm/test/CodeGen/PowerPC/future-check-features.ll
View File

@ -1,7 +1,7 @@
; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \
; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s