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Implement select handling for ARM fast-isel. 

llvm-svn: 116194
This commit is contained in:
Eric Christopher 2010-10-11 08:27:59 +00:00
parent 53afec4904
commit 511aa31965
1 changed files with 31 additions and 0 deletions
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31
llvm/lib/Target/ARM/ARMFastISel.cpp
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@ -128,6 +128,7 @@ class ARMFastISel : public FastISel {
virtual bool SelectFPToSI(const Instruction *I);
virtual bool SelectSDiv(const Instruction *I);
virtual bool SelectCall(const Instruction *I);
virtual bool SelectSelect(const Instruction *I);
// Utility routines.
private:
@ -1063,6 +1064,34 @@ bool ARMFastISel::SelectFPToSI(const Instruction *I) {
return true;
}
bool ARMFastISel::SelectSelect(const Instruction *I) {
EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
return false;
// Things need to be register sized for register moves.
if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
unsigned CondReg = getRegForValue(I->getOperand(0));
if (CondReg == 0) return false;
unsigned Op1Reg = getRegForValue(I->getOperand(1));
if (Op1Reg == 0) return false;
unsigned Op2Reg = getRegForValue(I->getOperand(2));
if (Op2Reg == 0) return false;
unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
.addReg(CondReg).addImm(1));
unsigned ResultReg = createResultReg(RC);
unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
.addReg(Op1Reg).addReg(Op2Reg)
.addImm(ARMCC::EQ).addReg(ARM::CPSR);
UpdateValueMap(I, ResultReg);
return true;
}
bool ARMFastISel::SelectSDiv(const Instruction *I) {
EVT VT;
const Type *Ty = I->getType();
@ -1490,6 +1519,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
return SelectSDiv(I);
case Instruction::Call:
return SelectCall(I);
case Instruction::Select:
return SelectSelect(I);
default: break;
}
return false;