forked from OSchip/llvm-project
rip out a ton of old instruction printing junk now that the
new instprinting logic is there. llvm-svn: 119111
This commit is contained in:
Chris Lattner
parent
f4a6a14c93
commit
510c66f549
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@ -55,13 +55,6 @@
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#include "InstPrinter/PPCInstPrinter.h"
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using namespace llvm;
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// This option tells the asmprinter to use the new (experimental) MCInstPrinter
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// path.
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static cl::opt<bool> UseInstPrinter("enable-ppc-inst-printer",
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cl::ReallyHidden
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, cl::init(true)
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);
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namespace {
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class PPCAsmPrinter : public AsmPrinter {
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protected:
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@ -77,74 +70,10 @@ namespace {
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return "PowerPC Assembly Printer";
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}
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unsigned enumRegToMachineReg(unsigned enumReg) {
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switch (enumReg) {
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default: llvm_unreachable("Unhandled register!");
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case PPC::CR0: return 0;
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case PPC::CR1: return 1;
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case PPC::CR2: return 2;
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case PPC::CR3: return 3;
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case PPC::CR4: return 4;
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case PPC::CR5: return 5;
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case PPC::CR6: return 6;
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case PPC::CR7: return 7;
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}
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llvm_unreachable(0);
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}
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/// printInstruction - This method is automatically generated by tablegen
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/// from the instruction set description. This method returns true if the
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/// machine instruction was sufficiently described to print it, otherwise it
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/// returns false.
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void printInstruction(const MachineInstr *MI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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virtual void EmitInstruction(const MachineInstr *MI);
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void printOp(const MachineOperand &MO, raw_ostream &O);
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/// stripRegisterPrefix - This method strips the character prefix from a
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/// register name so that only the number is left. Used by for linux asm.
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const char *stripRegisterPrefix(const char *RegName) {
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switch (RegName[0]) {
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case 'r':
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case 'f':
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case 'v': return RegName + 1;
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case 'c': if (RegName[1] == 'r') return RegName + 2;
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}
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return RegName;
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}
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/// printRegister - Print register according to target requirements.
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///
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void printRegister(const MachineOperand &MO, bool R0AsZero, raw_ostream &O){
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unsigned RegNo = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??");
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// If we should use 0 for R0.
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if (R0AsZero && RegNo == PPC::R0) {
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O << "0";
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return;
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}
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const char *RegName = getRegisterName(RegNo);
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// Linux assembler (Others?) does not take register mnemonics.
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// FIXME - What about special registers used in mfspr/mtspr?
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if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
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O << RegName;
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}
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (MO.isReg()) {
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printRegister(MO, false, O);
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} else if (MO.isImm()) {
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O << MO.getImm();
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} else {
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printOp(MO, O);
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}
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}
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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@ -153,192 +82,9 @@ namespace {
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O);
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void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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char value = MI->getOperand(OpNo).getImm();
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value = (value << (32-5)) >> (32-5);
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O << (int)value;
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}
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void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned char value = MI->getOperand(OpNo).getImm();
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assert(value <= 31 && "Invalid u5imm argument!");
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O << (unsigned int)value;
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}
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void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned char value = MI->getOperand(OpNo).getImm();
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assert(value <= 63 && "Invalid u6imm argument!");
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O << (unsigned int)value;
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}
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void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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O << (short)MI->getOperand(OpNo).getImm();
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}
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void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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O << (unsigned short)MI->getOperand(OpNo).getImm();
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}
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void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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O << (short)(MI->getOperand(OpNo).getImm()*4);
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} else {
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O << "lo16(";
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printOp(MI->getOperand(OpNo), O);
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if (TM.getRelocationModel() == Reloc::PIC_)
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O << "-\"L" << getFunctionNumber() << "$pb\")";
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else
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O << ')';
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}
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}
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void printBranchOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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// Branches can take an immediate operand. This is used by the branch
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// selection pass to print $+8, an eight byte displacement from the PC.
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if (MI->getOperand(OpNo).isImm()) {
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O << "$+" << MI->getOperand(OpNo).getImm()*4;
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} else {
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printOp(MI->getOperand(OpNo), O);
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}
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}
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void printCallOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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if (TM.getRelocationModel() != Reloc::Static) {
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if (MO.isGlobal()) {
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const GlobalValue *GV = MO.getGlobal();
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if (GV->isDeclaration() || GV->isWeakForLinker()) {
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// Dynamically-resolved functions need a stub for the function.
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MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$stub");
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MachineModuleInfoImpl::StubValueTy &StubSym =
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MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
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O << *Sym;
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return;
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}
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}
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if (MO.isSymbol()) {
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SmallString<128> TempNameStr;
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TempNameStr += StringRef(MO.getSymbolName());
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TempNameStr += StringRef("$stub");
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MCSymbol *Sym = GetExternalSymbolSymbol(TempNameStr.str());
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MachineModuleInfoImpl::StubValueTy &StubSym =
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MMI->getObjFileInfo<MachineModuleInfoMachO>().getFnStubEntry(Sym);
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if (StubSym.getPointer() == 0)
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StubSym = MachineModuleInfoImpl::
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StubValueTy(GetExternalSymbolSymbol(MO.getSymbolName()), true);
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O << *Sym;
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return;
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}
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}
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printOp(MI->getOperand(OpNo), O);
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}
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void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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O << (int)MI->getOperand(OpNo).getImm()*4;
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}
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void printPICLabel(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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O << "\"L" << getFunctionNumber() << "$pb\"\n";
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O << "\"L" << getFunctionNumber() << "$pb\":";
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}
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void printSymbolHi(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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printS16ImmOperand(MI, OpNo, O);
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} else {
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if (Subtarget.isDarwin()) O << "ha16(";
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printOp(MI->getOperand(OpNo), O);
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if (TM.getRelocationModel() == Reloc::PIC_)
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O << "-L" << getFunctionNumber() << "$pb";
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if (Subtarget.isDarwin())
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O << ')';
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else
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O << "@ha";
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}
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}
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void printSymbolLo(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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printS16ImmOperand(MI, OpNo, O);
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} else {
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if (Subtarget.isDarwin()) O << "lo16(";
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printOp(MI->getOperand(OpNo), O);
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if (TM.getRelocationModel() == Reloc::PIC_)
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O << "-L" << getFunctionNumber() << "$pb";
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if (Subtarget.isDarwin())
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O << ')';
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else
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O << "@l";
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}
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}
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void printcrbitm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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unsigned CCReg = MI->getOperand(OpNo).getReg();
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unsigned RegNo = enumRegToMachineReg(CCReg);
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O << (0x80 >> RegNo);
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}
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// The new addressing mode printers.
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void printMemRegImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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printSymbolLo(MI, OpNo, O);
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O << '(';
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if (MI->getOperand(OpNo+1).isReg() &&
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MI->getOperand(OpNo+1).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo+1, O);
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O << ')';
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}
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void printMemRegImmShifted(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm())
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printS16X4ImmOperand(MI, OpNo, O);
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else
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printSymbolLo(MI, OpNo, O);
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O << '(';
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if (MI->getOperand(OpNo+1).isReg() &&
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MI->getOperand(OpNo+1).getReg() == PPC::R0)
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O << "0";
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else
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printOperand(MI, OpNo+1, O);
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O << ')';
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}
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void printMemRegReg(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) {
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// When used as the base register, r0 reads constant zero rather than
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// the value contained in the register. For this reason, the darwin
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// assembler requires that we print r0 as 0 (no r) when used as the base.
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const MachineOperand &MO = MI->getOperand(OpNo);
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printRegister(MO, true, O);
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O << ", ";
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printOperand(MI, OpNo+1, O);
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}
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void printTOCEntryLabel(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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assert(MO.isGlobal());
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MCSymbol *Sym = Mang->getSymbol(MO.getGlobal());
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// Map symbol -> label of TOC entry.
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MCSymbol *&TOCEntry = TOC[Sym];
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if (TOCEntry == 0)
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TOCEntry = OutContext.
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GetOrCreateSymbol(StringRef(MAI->getPrivateGlobalPrefix()) +
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"C" + Twine(LabelID++));
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O << *TOCEntry << "@toc";
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}
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void printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier);
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const {
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MachineLocation Location;
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assert (MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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// Frame address. Currently handles register +- offset only.
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if (MI->getOperand(0).isReg() && MI->getOperand(2).isImm())
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Location.set(MI->getOperand(0).getReg(), MI->getOperand(2).getImm());
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@ -382,13 +128,35 @@ namespace {
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};
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} // end of anonymous namespace
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// Include the auto-generated portion of the assembly writer
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#include "PPCGenAsmWriter.inc"
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/// stripRegisterPrefix - This method strips the character prefix from a
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/// register name so that only the number is left. Used by for linux asm.
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static const char *stripRegisterPrefix(const char *RegName) {
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switch (RegName[0]) {
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case 'r':
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case 'f':
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case 'v': return RegName + 1;
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case 'c': if (RegName[1] == 'r') return RegName + 2;
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}
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return RegName;
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}
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void PPCAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) {
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void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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switch (MO.getType()) {
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case MachineOperand::MO_Register: {
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const char *RegName = PPCInstPrinter::getRegisterName(MO.getReg());
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// Linux assembler (Others?) does not take register mnemonics.
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// FIXME - What about special registers used in mfspr/mtspr?
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if (!Subtarget.isDarwin()) RegName = stripRegisterPrefix(RegName);
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O << RegName;
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return;
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}
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case MachineOperand::MO_Immediate:
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llvm_unreachable("printOp() does not handle immediate values");
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O << MO.getImm();
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return;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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@ -481,9 +249,7 @@ bool PPCAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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switch (ExtraCode[0]) {
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default: return true; // Unknown modifier.
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case 'c': // Don't print "$" before a global var name or constant.
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// PPC never has a prefix.
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printOperand(MI, OpNo, O);
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return false;
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break; // PPC never has a prefix.
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case 'L': // Write second word of DImode reference.
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// Verify that this operand has two consecutive registers.
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if (!MI->getOperand(OpNo).isReg() ||
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@ -515,183 +281,84 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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assert (MI->getOperand(OpNo).isReg());
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assert(MI->getOperand(OpNo).isReg());
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O << "0(";
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printOperand(MI, OpNo, O);
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O << ")";
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return false;
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}
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void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier){
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assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!");
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unsigned Code = MI->getOperand(OpNo).getImm();
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if (!strcmp(Modifier, "cc")) {
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switch ((PPC::Predicate)Code) {
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case PPC::PRED_ALWAYS: return; // Don't print anything for always.
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case PPC::PRED_LT: O << "lt"; return;
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case PPC::PRED_LE: O << "le"; return;
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case PPC::PRED_EQ: O << "eq"; return;
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case PPC::PRED_GE: O << "ge"; return;
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case PPC::PRED_GT: O << "gt"; return;
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case PPC::PRED_NE: O << "ne"; return;
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case PPC::PRED_UN: O << "un"; return;
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case PPC::PRED_NU: O << "nu"; return;
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}
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} else {
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assert(!strcmp(Modifier, "reg") &&
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"Need to specify 'cc' or 'reg' as predicate op modifier!");
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// Don't print the register for 'always'.
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if (Code == PPC::PRED_ALWAYS) return;
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printOperand(MI, OpNo+1, O);
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}
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}
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/// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to
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/// the current output stream.
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///
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void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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if (UseInstPrinter) {
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MCInst TmpInst;
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MCInst TmpInst;
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// Lower multi-instruction pseudo operations.
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switch (MI->getOpcode()) {
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default: break;
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case PPC::MovePCtoLR:
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case PPC::MovePCtoLR8: {
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// Transform %LR = MovePCtoLR
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// Into this, where the label is the PIC base:
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// bl L1$pb
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// L1$pb:
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MCSymbol *PICBase = MF->getPICBaseSymbol();
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// Lower multi-instruction pseudo operations.
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switch (MI->getOpcode()) {
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default: break;
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case PPC::MovePCtoLR:
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case PPC::MovePCtoLR8: {
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// Transform %LR = MovePCtoLR
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// Into this, where the label is the PIC base:
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// bl L1$pb
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// L1$pb:
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MCSymbol *PICBase = MF->getPICBaseSymbol();
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// Emit the 'bl'.
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TmpInst.setOpcode(PPC::BL_Darwin); // Darwin vs SVR4 doesn't matter here.
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// FIXME: We would like an efficient form for this, so we don't have to do
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// a lot of extra uniquing.
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TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::
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Create(PICBase, OutContext)));
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OutStreamer.EmitInstruction(TmpInst);
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// Emit the label.
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OutStreamer.EmitLabel(PICBase);
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return;
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}
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case PPC::LDtoc: {
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// Transform %X3 = LDtoc <ga:@min1>, %X2
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LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
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// Change the opcode to LD, and the global address operand to be a
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// reference to the TOC entry we will synthesize later.
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TmpInst.setOpcode(PPC::LD);
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const MachineOperand &MO = MI->getOperand(1);
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assert(MO.isGlobal());
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// Map symbol -> label of TOC entry.
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MCSymbol *&TOCEntry = TOC[Mang->getSymbol(MO.getGlobal())];
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if (TOCEntry == 0) {
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TOCEntry = OutContext.
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GetOrCreateSymbol(StringRef(MAI->getPrivateGlobalPrefix()) +
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"C" + Twine(LabelID++));
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}
|
||||
|
||||
const MCExpr *Exp =
|
||||
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
|
||||
OutContext);
|
||||
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
return;
|
||||
}
|
||||
|
||||
case PPC::MFCRpseud:
|
||||
// Transform: %R3 = MFCRpseud %CR7
|
||||
// Into: %R3 = MFCR ;; cr7
|
||||
OutStreamer.AddComment(getRegisterName(MI->getOperand(1).getReg()));
|
||||
TmpInst.setOpcode(PPC::MFCR);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
return;
|
||||
}
|
||||
|
||||
// Emit the 'bl'.
|
||||
TmpInst.setOpcode(PPC::BL_Darwin); // Darwin vs SVR4 doesn't matter here.
|
||||
|
||||
|
||||
// FIXME: We would like an efficient form for this, so we don't have to do
|
||||
// a lot of extra uniquing.
|
||||
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::
|
||||
Create(PICBase, OutContext)));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
|
||||
// Emit the label.
|
||||
OutStreamer.EmitLabel(PICBase);
|
||||
return;
|
||||
}
|
||||
case PPC::LDtoc: {
|
||||
// Transform %X3 = LDtoc <ga:@min1>, %X2
|
||||
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
|
||||
|
||||
// Change the opcode to LD, and the global address operand to be a
|
||||
// reference to the TOC entry we will synthesize later.
|
||||
TmpInst.setOpcode(PPC::LD);
|
||||
const MachineOperand &MO = MI->getOperand(1);
|
||||
assert(MO.isGlobal());
|
||||
|
||||
// Map symbol -> label of TOC entry.
|
||||
MCSymbol *&TOCEntry = TOC[Mang->getSymbol(MO.getGlobal())];
|
||||
if (TOCEntry == 0) {
|
||||
TOCEntry = OutContext.
|
||||
GetOrCreateSymbol(StringRef(MAI->getPrivateGlobalPrefix()) +
|
||||
"C" + Twine(LabelID++));
|
||||
}
|
||||
|
||||
const MCExpr *Exp =
|
||||
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
|
||||
OutContext);
|
||||
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
SmallString<128> Str;
|
||||
raw_svector_ostream O(Str);
|
||||
|
||||
if (MI->getOpcode() == TargetOpcode::DBG_VALUE) {
|
||||
unsigned NOps = MI->getNumOperands();
|
||||
assert(NOps==4);
|
||||
O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
|
||||
// cast away const; DIetc do not take const operands for some reason.
|
||||
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
|
||||
O << V.getName();
|
||||
O << " <- ";
|
||||
// Frame address. Currently handles register +- offset only.
|
||||
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
|
||||
O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 1, O);
|
||||
O << ']';
|
||||
O << "+";
|
||||
printOperand(MI, NOps-2, O);
|
||||
OutStreamer.EmitRawText(O.str());
|
||||
|
||||
case PPC::MFCRpseud:
|
||||
// Transform: %R3 = MFCRpseud %CR7
|
||||
// Into: %R3 = MFCR ;; cr7
|
||||
OutStreamer.AddComment(PPCInstPrinter::
|
||||
getRegisterName(MI->getOperand(1).getReg()));
|
||||
TmpInst.setOpcode(PPC::MFCR);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
return;
|
||||
}
|
||||
// Check for slwi/srwi mnemonics.
|
||||
if (MI->getOpcode() == PPC::RLWINM) {
|
||||
unsigned char SH = MI->getOperand(2).getImm();
|
||||
unsigned char MB = MI->getOperand(3).getImm();
|
||||
unsigned char ME = MI->getOperand(4).getImm();
|
||||
bool useSubstituteMnemonic = false;
|
||||
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
|
||||
O << "\tslwi "; useSubstituteMnemonic = true;
|
||||
}
|
||||
if (SH <= 31 && MB == (32-SH) && ME == 31) {
|
||||
O << "\tsrwi "; useSubstituteMnemonic = true;
|
||||
SH = 32-SH;
|
||||
}
|
||||
if (useSubstituteMnemonic) {
|
||||
printOperand(MI, 0, O);
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
O << ", " << (unsigned int)SH;
|
||||
OutStreamer.EmitRawText(O.str());
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
|
||||
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
|
||||
O << "\tmr ";
|
||||
printOperand(MI, 0, O);
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
OutStreamer.EmitRawText(O.str());
|
||||
return;
|
||||
}
|
||||
|
||||
if (MI->getOpcode() == PPC::RLDICR) {
|
||||
unsigned char SH = MI->getOperand(2).getImm();
|
||||
unsigned char ME = MI->getOperand(3).getImm();
|
||||
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
|
||||
if (63-SH == ME) {
|
||||
O << "\tsldi ";
|
||||
printOperand(MI, 0, O);
|
||||
O << ", ";
|
||||
printOperand(MI, 1, O);
|
||||
O << ", " << (unsigned int)SH;
|
||||
OutStreamer.EmitRawText(O.str());
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
printInstruction(MI, O);
|
||||
OutStreamer.EmitRawText(O.str());
|
||||
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
|
||||
void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() {
|
||||
|
|
|
|||
Loading…
Reference in New Issue