From 50ded90072fa9504f93436951319d1a07169e1aa Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen@arm.com>
Date: Sun, 29 Apr 2018 17:33:38 +0000
Subject: [PATCH] [AArch64][SVE] Asm: Support for gather LD1/LDFF1 (vector +
 imm) load instructions.

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46120

llvm-svn: 331145
---
 .../lib/Target/AArch64/AArch64InstrFormats.td | 29 ++++++++
 .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 30 ++++++++
 .../AArch64/AsmParser/AArch64AsmParser.cpp    | 31 ++++++--
 llvm/lib/Target/AArch64/SVEInstrFormats.td    | 70 +++++++++++++++++++
 llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s   | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1b.s               | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s   | 39 +++++++++++
 llvm/test/MC/AArch64/SVE/ld1d.s               | 12 ++++
 llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s   | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ld1h.s               | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s  | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1sb.s              | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s  | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ld1sh.s              | 24 +++++++
 llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s  | 39 +++++++++++
 llvm/test/MC/AArch64/SVE/ld1sw.s              | 12 ++++
 llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s   | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ld1w.s               | 24 +++++++
 llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s | 24 +++++++
 llvm/test/MC/AArch64/SVE/ldff1b.s             | 24 +++++++
 llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s | 39 +++++++++++
 llvm/test/MC/AArch64/SVE/ldff1d.s             | 12 ++++
 llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ldff1h.s             | 24 +++++++
 .../test/MC/AArch64/SVE/ldff1sb-diagnostics.s | 24 +++++++
 llvm/test/MC/AArch64/SVE/ldff1sb.s            | 24 +++++++
 .../test/MC/AArch64/SVE/ldff1sh-diagnostics.s | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ldff1sh.s            | 24 +++++++
 .../test/MC/AArch64/SVE/ldff1sw-diagnostics.s | 39 +++++++++++
 llvm/test/MC/AArch64/SVE/ldff1sw.s            | 12 ++++
 llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s | 54 ++++++++++++++
 llvm/test/MC/AArch64/SVE/ldff1w.s             | 24 +++++++
 32 files changed, 1020 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index f1fd6c958e9f..8d06fd8b70f6 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -196,6 +196,13 @@ def SImm10s8Operand : AsmOperandClass {
   let PredicateMethod = "isSImmScaled<10, 8>";
 }
 
+class UImmScaledMemoryIndexed<int Width, int Scale> : AsmOperandClass {
+  let Name = "UImm" # Width # "s" # Scale;
+  let DiagnosticType = "InvalidMemoryIndexed" # Scale # "UImm" # Width;
+  let RenderMethod = "addImmScaledOperands<" # Scale # ">";
+  let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ">";
+}
+
 //===----------------------------------------------------------------------===//
 // Operand Definitions.
 //
@@ -291,6 +298,28 @@ def am_indexed7s32  : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S32", []>;
 def am_indexed7s64  : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S64", []>;
 def am_indexed7s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S128", []>;
 
+// uimm5sN predicate - True if the immediate is a multiple of N in the range
+// [0 * N, 32 * N].
+def UImm5s2Operand : UImmScaledMemoryIndexed<5, 2>;
+def UImm5s4Operand : UImmScaledMemoryIndexed<5, 4>;
+def UImm5s8Operand : UImmScaledMemoryIndexed<5, 8>;
+
+def uimm5s2 : Operand<i64>, ImmLeaf<i64,
+                [{ return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); }]> {
+  let ParserMatchClass = UImm5s2Operand;
+  let PrintMethod = "printImmScale<2>";
+}
+def uimm5s4 : Operand<i64>, ImmLeaf<i64,
+                [{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }]> {
+  let ParserMatchClass = UImm5s4Operand;
+  let PrintMethod = "printImmScale<4>";
+}
+def uimm5s8 : Operand<i64>, ImmLeaf<i64,
+                [{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }]> {
+  let ParserMatchClass = UImm5s8Operand;
+  let PrintMethod = "printImmScale<8>";
+}
+
 class AsmImmRange<int Low, int High> : AsmOperandClass {
   let Name = "Imm" # Low # "_" # High;
   let DiagnosticType = "InvalidImm" # Low # "_" # High;
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 115fa26f846e..32dc477a8bf1 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -128,6 +128,36 @@ let Predicates = [HasSVE] in {
   defm GLD1W      : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w",    ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
   defm GLDFF1W    : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w",  ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
 
+  // Gathers using scaled 32-bit pointers with offset, e.g.
+  //    ld1h z0.s, p0/z, [z0.s, #16]
+  defm GLD1SB_S   : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb",   imm0_31>;
+  defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
+  defm GLD1B_S    : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b",    imm0_31>;
+  defm GLDFF1B_S  : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b",  imm0_31>;
+  defm GLD1SH_S   : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh",   uimm5s2>;
+  defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;
+  defm GLD1H_S    : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h",    uimm5s2>;
+  defm GLDFF1H_S  : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h",  uimm5s2>;
+  defm GLD1W      : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w",    uimm5s4>;
+  defm GLDFF1W    : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w",  uimm5s4>;
+
+  // Gathers using scaled 64-bit pointers with offset, e.g.
+  //    ld1h z0.d, p0/z, [z0.d, #16]
+  defm GLD1SB_D   : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb",   imm0_31>;
+  defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
+  defm GLD1B_D    : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b",    imm0_31>;
+  defm GLDFF1B_D  : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b",  imm0_31>;
+  defm GLD1SH_D   : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh",   uimm5s2>;
+  defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;
+  defm GLD1H_D    : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h",    uimm5s2>;
+  defm GLDFF1H_D  : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h",  uimm5s2>;
+  defm GLD1SW_D   : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw",   uimm5s4>;
+  defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
+  defm GLD1W_D    : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w",    uimm5s4>;
+  defm GLDFF1W_D  : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w",  uimm5s4>;
+  defm GLD1D      : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d",    uimm5s8>;
+  defm GLDFF1D    : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d",  uimm5s8>;
+
   // Gathers using unscaled 64-bit offsets, e.g.
   //    ld1h z0.d, p0/z, [x0, z0.d]
   defm GLD1SB_D   : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 2f042cd3df61..b64ae4e0ed21 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -506,8 +506,16 @@ public:
 
   template <int Width> bool isSImm() const { return isSImmScaled<Width, 1>(); }
 
+  template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
+    return isImmScaled<Bits, Scale>(true);
+  }
+
+  template <int Bits, int Scale> DiagnosticPredicate isUImmScaled() const {
+    return isImmScaled<Bits, Scale>(false);
+  }
+
   template <int Bits, int Scale>
-  DiagnosticPredicate isSImmScaled() const {
+  DiagnosticPredicate isImmScaled(bool Signed) const {
     if (!isImm())
       return DiagnosticPredicateTy::NoMatch;
 
@@ -515,9 +523,15 @@ public:
     if (!MCE)
       return DiagnosticPredicateTy::NoMatch;
 
-    int64_t Shift = Bits - 1;
-    int64_t MinVal = (int64_t(1) << Shift) * -Scale;
-    int64_t MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
+    int64_t MinVal, MaxVal;
+    if (Signed) {
+      int64_t Shift = Bits - 1;
+      MinVal = (int64_t(1) << Shift) * -Scale;
+      MaxVal = ((int64_t(1) << Shift) - 1) * Scale;
+    } else {
+      MinVal = 0;
+      MaxVal = ((int64_t(1) << Bits) - 1) * Scale;
+    }
 
     int64_t Val = MCE->getValue();
     if (Val >= MinVal && Val <= MaxVal && (Val % Scale) == 0)
@@ -3754,6 +3768,12 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
     return Error(Loc, "index must be a multiple of 8 in range [-512, 504].");
   case Match_InvalidMemoryIndexed16SImm7:
     return Error(Loc, "index must be a multiple of 16 in range [-1024, 1008].");
+  case Match_InvalidMemoryIndexed8UImm5:
+    return Error(Loc, "index must be a multiple of 8 in range [0, 248].");
+  case Match_InvalidMemoryIndexed4UImm5:
+    return Error(Loc, "index must be a multiple of 4 in range [0, 124].");
+  case Match_InvalidMemoryIndexed2UImm5:
+    return Error(Loc, "index must be a multiple of 2 in range [0, 62].");
   case Match_InvalidMemoryWExtend8:
     return Error(Loc,
                  "expected 'uxtw' or 'sxtw' with optional shift of #0");
@@ -4313,6 +4333,9 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMemoryIndexed4SImm7:
   case Match_InvalidMemoryIndexed8SImm7:
   case Match_InvalidMemoryIndexed16SImm7:
+  case Match_InvalidMemoryIndexed8UImm5:
+  case Match_InvalidMemoryIndexed4UImm5:
+  case Match_InvalidMemoryIndexed2UImm5:
   case Match_InvalidMemoryIndexedSImm6:
   case Match_InvalidMemoryIndexedSImm5:
   case Match_InvalidMemoryIndexedSImm9:
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 024c61285f0e..63613663fc14 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -818,6 +818,41 @@ multiclass sve_mem_32b_gld_vs_32_unscaled<bits<4> opc, string asm,
 }
 
 
+class sve_mem_32b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
+: I<(outs Z_s:$Zt), (ins PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5),
+  asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Zn;
+  bits<5> Zt;
+  bits<5> imm5;
+  let Inst{31-25} = 0b1000010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22-21} = 0b01;
+  let Inst{20-16} = imm5;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_32b_gld_vi_32_ptrs<bits<4> opc, string asm, Operand imm_ty> {
+  def _IMM_REAL : sve_mem_32b_gld_vi<opc, asm, imm_ty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR32:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, imm_ty:$imm5), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_s:$Zt, PPR3bAny:$Pg, ZPR32:$Zn, 0), 1>;
+}
+
 //===----------------------------------------------------------------------===//
 // SVE Memory - 64-bit Gather Group
 //===----------------------------------------------------------------------===//
@@ -889,3 +924,38 @@ multiclass sve_mem_64b_gld_vs2_64_unscaled<bits<4> opc, string asm> {
   def : InstAlias<asm # "\t$Zt, $Pg/z, [$Rn, $Zm]",
                   (!cast<Instruction>(NAME # _REAL) ZPR64:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, ZPR64ExtLSL8:$Zm), 0>;
 }
+
+class sve_mem_64b_gld_vi<bits<4> opc, string asm, Operand imm_ty>
+: I<(outs Z_d:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5),
+  asm, "\t$Zt, $Pg/z, [$Zn, $imm5]",
+  "",
+  []>, Sched<[]> {
+  bits<3> Pg;
+  bits<5> Zn;
+  bits<5> Zt;
+  bits<5> imm5;
+  let Inst{31-25} = 0b1100010;
+  let Inst{24-23} = opc{3-2};
+  let Inst{22-21} = 0b01;
+  let Inst{20-16} = imm5;
+  let Inst{15}    = 0b1;
+  let Inst{14-13} = opc{1-0};
+  let Inst{12-10} = Pg;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zt;
+
+  let mayLoad = 1;
+  let Defs = !if(!eq(opc{0}, 1), [FFR], []);
+  let Uses = !if(!eq(opc{0}, 1), [FFR], []);
+}
+
+multiclass sve_mem_64b_gld_vi_64_ptrs<bits<4> opc, string asm, Operand imm_ty> {
+  def _IMM_REAL : sve_mem_64b_gld_vi<opc, asm, imm_ty>;
+
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+                  (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn, $imm5]",
+                 (!cast<Instruction>(NAME # _IMM_REAL) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
+  def : InstAlias<asm # "\t$Zt, $Pg/z, [$Zn]",
+                  (!cast<Instruction>(NAME # _IMM_REAL) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
+}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
index a1b4e0f1297a..c62cf1af981b 100644
--- a/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s
@@ -153,3 +153,27 @@ ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1b z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1b z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1b z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1b z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1b.s b/llvm/test/MC/AArch64/SVE/ld1b.s
index 226048fd4d4e..34ac5a887aba 100644
--- a/llvm/test/MC/AArch64/SVE/ld1b.s
+++ b/llvm/test/MC/AArch64/SVE/ld1b.s
@@ -168,3 +168,27 @@ ld1b    { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x55,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 55 55 c4 <unknown>
+
+ld1b    { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ld1b    { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f 84 <unknown>
+
+ld1b    { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1b    { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 84 <unknown>
+
+ld1b    { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ld1b    { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f c4 <unknown>
+
+ld1b    { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1b    { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
index 9be718071cc2..87cd642d5b2e 100644
--- a/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s
@@ -93,3 +93,42 @@ ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ld1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1d z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.s, p0/z, [z0.s, #8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1d z0.s, p0/z, [z0.s, #8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #-8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #249]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #249]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1d z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ld1d z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1d.s b/llvm/test/MC/AArch64/SVE/ld1d.s
index 0994abc5da7e..59dce412959d 100644
--- a/llvm/test/MC/AArch64/SVE/ld1d.s
+++ b/llvm/test/MC/AArch64/SVE/ld1d.s
@@ -78,3 +78,15 @@ ld1d    { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 e0 c5 <unknown>
+
+ld1d    { z31.d }, p7/z, [z31.d, #248]
+// CHECK-INST: ld1d    { z31.d }, p7/z, [z31.d, #248]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf c5 <unknown>
+
+ld1d    { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1d    { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 c5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
index a9d89926bf77..53a26a1d9dad 100644
--- a/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s
@@ -138,3 +138,57 @@ ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1h z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1h z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1h z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1h.s b/llvm/test/MC/AArch64/SVE/ld1h.s
index 0a1e14203511..41ee04cb79b6 100644
--- a/llvm/test/MC/AArch64/SVE/ld1h.s
+++ b/llvm/test/MC/AArch64/SVE/ld1h.s
@@ -162,3 +162,27 @@ ld1h    { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x40,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 e0 c4 <unknown>
+
+ld1h    { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ld1h    { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf 84 <unknown>
+
+ld1h    { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1h    { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 84 <unknown>
+
+ld1h    { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ld1h    { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xdf,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df bf c4 <unknown>
+
+ld1h    { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1h    { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 a0 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
index 3431099a8715..c136db1b062a 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s
@@ -151,3 +151,27 @@ ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sb z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ld1sb z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sb.s b/llvm/test/MC/AArch64/SVE/ld1sb.s
index a583158fd497..7f12189ea088 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sb.s
@@ -138,3 +138,27 @@ ld1sb   { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x15,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 15 55 c4 <unknown>
+
+ld1sb   { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ld1sb   { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f 84 <unknown>
+
+ld1sb   { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1sb   { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0x80,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 84 <unknown>
+
+ld1sb   { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ld1sb   { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f c4 <unknown>
+
+ld1sb   { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sb   { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
index bbaf666b3c09..1df432c49e32 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s
@@ -137,3 +137,57 @@ ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sh z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sh.s b/llvm/test/MC/AArch64/SVE/ld1sh.s
index fa5aeee8e46d..c329724e254d 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sh.s
@@ -132,3 +132,27 @@ ld1sh   { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x00,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 e0 c4 <unknown>
+
+ld1sh   { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ld1sh   { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0x9f,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f bf 84 <unknown>
+
+ld1sh   { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1sh   { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a0 84 <unknown>
+
+ld1sh   { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ld1sh   { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0x9f,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f bf c4 <unknown>
+
+ld1sh   { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sh   { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 a0 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
index 0363e0b3169e..b58b41db88fb 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s
@@ -127,3 +127,42 @@ ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1sw z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.s, p0/z, [z0.s, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1sw z0.s, p0/z, [z0.s, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1sw z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1sw z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1sw.s b/llvm/test/MC/AArch64/SVE/ld1sw.s
index 60c38c6463e1..a8b3f18c960b 100644
--- a/llvm/test/MC/AArch64/SVE/ld1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ld1sw.s
@@ -78,3 +78,15 @@ ld1sw   { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x00,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 00 60 c5 <unknown>
+
+ld1sw   { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ld1sw   { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0x9f,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff 9f 3f c5 <unknown>
+
+ld1sw   { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1sw   { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 20 c5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
index 86e12f57a338..8a8fa13a215a 100644
--- a/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s
@@ -123,3 +123,57 @@ ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ld1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ld1w z0.s, p0/z, [z0.s, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1w z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ld1w z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ld1w.s b/llvm/test/MC/AArch64/SVE/ld1w.s
index f9926f33b68c..720260f41a73 100644
--- a/llvm/test/MC/AArch64/SVE/ld1w.s
+++ b/llvm/test/MC/AArch64/SVE/ld1w.s
@@ -132,3 +132,27 @@ ld1w    { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x40,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 40 60 c5 <unknown>
+
+ld1w    { z31.s }, p7/z, [z31.s, #124]
+// CHECK-INST: ld1w    { z31.s }, p7/z, [z31.s, #124]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f 85 <unknown>
+
+ld1w    { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ld1w    { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 85 <unknown>
+
+ld1w    { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ld1w    { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xdf,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff df 3f c5 <unknown>
+
+ld1w    { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ld1w    { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c0 20 c5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s
index 19988743c9a9..1870a3e9b945 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1b-diagnostics.s
@@ -88,3 +88,27 @@ ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1b z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1b z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1b z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1b z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1b.s b/llvm/test/MC/AArch64/SVE/ldff1b.s
index 6c23e2909b29..ca1192908c97 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1b.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1b.s
@@ -102,3 +102,27 @@ ldff1b  { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x75,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 75 55 c4 <unknown>
+
+ldff1b  { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ldff1b  { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f 84 <unknown>
+
+ldff1b  { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1b  { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 84 <unknown>
+
+ldff1b  { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ldff1b  { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f c4 <unknown>
+
+ldff1b  { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1b  { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
index 60ab31faadad..f180983e47c1 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1d-diagnostics.s
@@ -72,3 +72,42 @@ ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected #imm after shift specifier
 // CHECK-NEXT: ldff1d z0.d, p0/z, [x0, z0.d, lsl]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1d z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.s, p0/z, [z0.s, #8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1d z0.s, p0/z, [z0.s, #8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #-8]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-8]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #249]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #249]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #256]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #256]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1d z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 8 in range [0, 248].
+// CHECK-NEXT: ldff1d z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1d.s b/llvm/test/MC/AArch64/SVE/ldff1d.s
index f13992418a43..4ba710b9050e 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1d.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1d.s
@@ -60,3 +60,15 @@ ldff1d  { z0.d }, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 c5 <unknown>
+
+ldff1d  { z31.d }, p7/z, [z31.d, #248]
+// CHECK-INST: ldff1d  { z31.d }, p7/z, [z31.d, #248]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf c5 <unknown>
+
+ldff1d  { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1d  { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 c5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s
index 5bab001fddc2..f23b7683a994 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1h-diagnostics.s
@@ -87,3 +87,57 @@ ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1h z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1h z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1h z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1h z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1h.s b/llvm/test/MC/AArch64/SVE/ldff1h.s
index 6f28928a6b6b..d4e4ebaa4e8c 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1h.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1h.s
@@ -120,3 +120,27 @@ ldff1h  { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x60,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 e0 c4 <unknown>
+
+ldff1h  { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ldff1h  { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf 84 <unknown>
+
+ldff1h  { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1h  { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 84 <unknown>
+
+ldff1h  { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ldff1h  { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xff,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff bf c4 <unknown>
+
+ldff1h  { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1h  { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 a0 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
index 91164593e748..412761347ccf 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sb-diagnostics.s
@@ -91,3 +91,27 @@ ldff1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sb z0.d, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.s, p0/z, [z0.s, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.s, p0/z, [z0.s, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sb z0.d, p0/z, [z0.d, #32]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31].
+// CHECK-NEXT: ldff1sb z0.d, p0/z, [z0.d, #32]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sb.s b/llvm/test/MC/AArch64/SVE/ldff1sb.s
index ef2ecf284fe0..fbab69927bbe 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sb.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sb.s
@@ -90,3 +90,27 @@ ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]
 // CHECK-ENCODING: [0x55,0x35,0x55,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 55 35 55 c4 <unknown>
+
+ldff1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-INST: ldff1sb { z31.s }, p7/z, [z31.s, #31]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f 84 <unknown>
+
+ldff1sb { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1sb { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 84 <unknown>
+
+ldff1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-INST: ldff1sb { z31.d }, p7/z, [z31.d, #31]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f c4 <unknown>
+
+ldff1sb { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sb { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
index aa056777190a..70e13ca031ac 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sh-diagnostics.s
@@ -81,3 +81,57 @@ ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #-2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #63]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #63]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #64]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #64]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sh z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
+// CHECK-NEXT: ldff1sh z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sh.s b/llvm/test/MC/AArch64/SVE/ldff1sh.s
index b81608e16d4a..3444840334f9 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sh.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sh.s
@@ -102,3 +102,27 @@ ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]
 // CHECK-ENCODING: [0x00,0x20,0xe0,0xc4]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 e0 c4 <unknown>
+
+ldff1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-INST: ldff1sh { z31.s }, p7/z, [z31.s, #62]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf 84 <unknown>
+
+ldff1sh { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1sh { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0x84]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 84 <unknown>
+
+ldff1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-INST: ldff1sh { z31.d }, p7/z, [z31.d, #62]
+// CHECK-ENCODING: [0xff,0xbf,0xbf,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf bf c4 <unknown>
+
+ldff1sh { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sh { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0xa0,0xc4]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 a0 c4 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
index 765b3ee135c1..3b1c9a14ef95 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sw-diagnostics.s
@@ -82,3 +82,42 @@ ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1sw z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1sw z0.s, p0/z, [z0.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.s, p0/z, [z0.s, #4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ldff1sw z0.s, p0/z, [z0.s, #4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1sw z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1sw z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1sw.s b/llvm/test/MC/AArch64/SVE/ldff1sw.s
index e3185c49864f..0ee1b9c01c7c 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1sw.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1sw.s
@@ -60,3 +60,15 @@ ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x20,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 20 60 c5 <unknown>
+
+ldff1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ldff1sw { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xbf,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff bf 3f c5 <unknown>
+
+ldff1sw { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1sw { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 a0 20 c5 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
index cdf12e66906d..9b5b2a17fe00 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1w-diagnostics.s
@@ -87,3 +87,57 @@ ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'
 // CHECK-NEXT: ldff1w z0.d, p0/z, [x0, z0.d, sxtw #3]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid vector + immediate addressing modes
+
+ldff1w z0.s, p0/z, [z0.s, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.s, p0/z, [z0.s, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.s, p0/z, [z0.s, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #-4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #-4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #125]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #125]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #128]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #128]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ldff1w z0.d, p0/z, [z0.d, #3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 4 in range [0, 124].
+// CHECK-NEXT: ldff1w z0.d, p0/z, [z0.d, #3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/ldff1w.s b/llvm/test/MC/AArch64/SVE/ldff1w.s
index 49e57ec41c70..019974316260 100644
--- a/llvm/test/MC/AArch64/SVE/ldff1w.s
+++ b/llvm/test/MC/AArch64/SVE/ldff1w.s
@@ -102,3 +102,27 @@ ldff1w  { z0.d }, p0/z, [x0, z0.d, sxtw #2]
 // CHECK-ENCODING: [0x00,0x60,0x60,0xc5]
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: 00 60 60 c5 <unknown>
+
+ldff1w  { z31.s }, p7/z, [z31.s, #124]
+// CHECK-INST: ldff1w  { z31.s }, p7/z, [z31.s, #124]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f 85 <unknown>
+
+ldff1w  { z0.s }, p0/z, [z0.s]
+// CHECK-INST: ldff1w  { z0.s }, p0/z, [z0.s]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0x85]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 85 <unknown>
+
+ldff1w  { z31.d }, p7/z, [z31.d, #124]
+// CHECK-INST: ldff1w  { z31.d }, p7/z, [z31.d, #124]
+// CHECK-ENCODING: [0xff,0xff,0x3f,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: ff ff 3f c5 <unknown>
+
+ldff1w  { z0.d }, p0/z, [z0.d]
+// CHECK-INST: ldff1w  { z0.d }, p0/z, [z0.d]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0xc5]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 e0 20 c5 <unknown>