maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[GlobalISel] Simplify RegBankSelect 

Save the instruction list of a block before selecting banks.
This allows to cope with moved instructions, even if they are reordered
or splitted into multiple basic blocks.

Differential Revision: https://reviews.llvm.org/D111223
This commit is contained in:
Neubauer, Sebastian 2021-10-25 16:11:42 +02:00
parent 5f4980f004
commit 50d8d963e3
1 changed files with 5 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
View File

@ -699,11 +699,11 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
// Set a sensible insertion point so that subsequent calls to
// MIRBuilder.
MIRBuilder.setMBB(*MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), End = MBB->end();
MII != End;) {
// MI might be invalidated by the assignment, so move the
// iterator before hand.
MachineInstr &MI = *MII++;
SmallVector<MachineInstr *> WorkList(
make_pointer_range(reverse(MBB->instrs())));
while (!WorkList.empty()) {
MachineInstr &MI = *WorkList.pop_back_val();
// Ignore target-specific post-isel instructions: they should use proper
// regclasses.
@ -728,18 +728,6 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
"unable to map instruction", MI);
return false;
}
// It's possible the mapping changed control flow, and moved the following
// instruction to a new block, so figure out the new parent.
if (MII != End) {
MachineBasicBlock *NextInstBB = MII->getParent();
if (NextInstBB != MBB) {
LLVM_DEBUG(dbgs() << "Instruction mapping changed control flow\n");
MBB = NextInstBB;
MIRBuilder.setMBB(*MBB);
End = MBB->end();
}
}
}
}