forked from OSchip/llvm-project
[lanai] Add lowering for SETCCE i32.
* Add lowering for SETCCE i32. * Add test to check lowering of i64 compares uses SETCCE expansion (outside of EQ and NE). * Fix select.ll test and immediate form selection for RI operations. llvm-svn: 266802
This commit is contained in:
Jacques Pienaar
parent
b4b27230bf
commit
50d4e98905
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@ -71,6 +71,7 @@ LanaiTargetLowering::LanaiTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BRCOND, MVT::Other, Expand);
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setOperationAction(ISD::SETCC, MVT::i32, Custom);
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setOperationAction(ISD::SETCCE, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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@ -172,6 +173,8 @@ SDValue LanaiTargetLowering::LowerOperation(SDValue Op,
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return LowerSELECT_CC(Op, DAG);
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case ISD::SETCC:
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return LowerSETCC(Op, DAG);
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case ISD::SETCCE:
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return LowerSETCCE(Op, DAG);
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case ISD::SRL_PARTS:
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return LowerSRL_PARTS(Op, DAG);
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case ISD::VASTART:
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@ -779,9 +782,10 @@ SDValue LanaiTargetLowering::LowerCallResult(
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// Custom Lowerings
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//===----------------------------------------------------------------------===//
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static LPCC::CondCode IntCondCCodeToICC(ISD::CondCode SetCCOpcode, SDLoc DL,
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SDValue &LHS, SDValue &RHS,
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SelectionDAG &DAG) {
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static LPCC::CondCode IntCondCCodeToICC(SDValue CC, SDLoc DL, SDValue &LHS,
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SDValue &RHS, SelectionDAG &DAG) {
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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// For integer, only the SETEQ, SETNE, SETLT, SETLE, SETGT, SETGE, SETULT,
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// SETULE, SETUGT, and SETUGE opcodes are used (see CodeGen/ISDOpcodes.h)
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// and Lanai only supports integer comparisons, so only provide definitions
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@ -845,14 +849,14 @@ static LPCC::CondCode IntCondCCodeToICC(ISD::CondCode SetCCOpcode, SDLoc DL,
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SDValue LanaiTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
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SDValue Chain = Op.getOperand(0);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
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SDValue Cond = Op.getOperand(1);
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SDValue LHS = Op.getOperand(2);
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SDValue RHS = Op.getOperand(3);
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SDValue Dest = Op.getOperand(4);
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SDLoc DL(Op);
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SDValue TargetCC =
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DAG.getConstant(IntCondCCodeToICC(CC, DL, LHS, RHS, DAG), DL, MVT::i32);
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LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
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SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
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SDValue Flag =
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DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
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@ -946,14 +950,27 @@ SDValue LanaiTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
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return Res;
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}
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SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue Carry = Op.getOperand(2);
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SDValue Cond = Op.getOperand(3);
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SDLoc DL(Op);
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LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
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SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
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SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
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return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
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}
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SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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SDValue Cond = Op.getOperand(2);
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SDLoc DL(Op);
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SDValue TargetCC =
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DAG.getConstant(IntCondCCodeToICC(CC, DL, LHS, RHS, DAG), DL, MVT::i32);
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LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
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SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
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SDValue Flag =
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DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
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@ -966,11 +983,11 @@ SDValue LanaiTargetLowering::LowerSELECT_CC(SDValue Op,
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SDValue RHS = Op.getOperand(1);
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SDValue TrueV = Op.getOperand(2);
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SDValue FalseV = Op.getOperand(3);
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDValue Cond = Op.getOperand(4);
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SDLoc DL(Op);
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SDValue TargetCC =
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DAG.getConstant(IntCondCCodeToICC(CC, DL, LHS, RHS, DAG), DL, MVT::i32);
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LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, LHS, RHS, DAG);
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SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
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SDValue Flag =
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DAG.getNode(LanaiISD::SET_FLAG, DL, MVT::Glue, LHS, RHS, TargetCC);
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@ -1084,6 +1101,8 @@ const char *LanaiTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "LanaiISD::SELECT_CC";
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case LanaiISD::SETCC:
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return "LanaiISD::SETCC";
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case LanaiISD::SUBBF:
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return "LanaiISD::SUBBF";
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case LanaiISD::SET_FLAG:
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return "LanaiISD::SET_FLAG";
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case LanaiISD::BR_CC:
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@ -38,12 +38,15 @@ enum {
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// is condition code and operand 4 is flag operand.
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SELECT_CC,
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// SETCC - Store the conditional to a register
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// SETCC - Store the conditional code to a register.
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SETCC,
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// SET_FLAG - Set flag compare
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// SET_FLAG - Set flag compare.
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SET_FLAG,
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// SUBBF - Subtract with borrow that sets flags.
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SUBBF,
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// BR_CC - Used to glue together a conditional branch and comparison
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BR_CC,
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@ -51,11 +54,11 @@ enum {
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// and TargetGlobalAddress.
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Wrapper,
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// Get the Higher/Lower 16 bits from a 32-bit immediate
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// Get the Higher/Lower 16 bits from a 32-bit immediate.
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HI,
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LO,
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// Small 21-bit immediate in global memory
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// Small 21-bit immediate in global memory.
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SMALL
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};
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} // namespace LanaiISD
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@ -87,6 +90,7 @@ public:
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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@ -41,12 +41,14 @@ def Call : SDNode<"LanaiISD::CALL", SDT_LanaiCall,
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SDNPVariadic]>;
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def RetFlag : SDNode<"LanaiISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_LanaiCallSeqStart,
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def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_LanaiCallSeqStart,
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[SDNPHasChain, SDNPOutGlue]>;
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def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_LanaiCallSeqEnd,
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def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_LanaiCallSeqEnd,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def LanaiSetFlag : SDNode<"LanaiISD::SET_FLAG", SDT_LanaiSetFlag,
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[SDNPOutGlue]>;
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def LanaiSubbF : SDNode<"LanaiISD::SUBBF", SDT_LanaiSetFlag,
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[SDNPOutGlue, SDNPInGlue]>;
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def LanaiBrCC : SDNode<"LanaiISD::BR_CC", SDT_LanaiBrCC,
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[SDNPHasChain, SDNPInGlue]>;
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def LanaiSelectCC : SDNode<"LanaiISD::SELECT_CC", SDT_LanaiSelectCC,
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@ -315,13 +317,13 @@ multiclass ALUlogic<bits<3> subOp, string AsmStr, SDNode OpNode,
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// Non flag setting ALU operations
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let isAsCheapAsAMove = 1, F = 0 in {
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let isCommutable = 1 in {
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defm ADD_ : ALUarith<0b000, "add", add, i32lo16s, i32hi16>;
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defm ADD_ : ALUarith<0b000, "add", add, i32lo16z, i32hi16>;
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}
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defm SUB_ : ALUarith<0b010, "sub", sub, i32lo16s, i32hi16>;
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defm SUB_ : ALUarith<0b010, "sub", sub, i32lo16z, i32hi16>;
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let isCommutable = 1 in {
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defm AND_ : ALUlogic<0b100, "and", and, i32lo16and, i32hi16and>;
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defm OR_ : ALUlogic<0b101, "or", or, i32lo16z, i32hi16>;
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defm XOR_ : ALUlogic<0b110, "xor", xor, i32lo16s, i32hi16>;
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defm XOR_ : ALUlogic<0b110, "xor", xor, i32lo16z, i32hi16>;
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}
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}
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@ -348,8 +350,8 @@ def : Pat<(sub GPR:$Rs1, i32neg16:$imm),
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// Flag (incl. carry) setting addition and subtraction
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let F = 1, Defs = [SR] in {
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defm ADD_F_ : ALUarith<0b000, "add.f", addc, i32lo16s, i32hi16>;
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defm SUB_F_ : ALUarith<0b010, "sub.f", subc, i32lo16s, i32hi16>;
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defm ADD_F_ : ALUarith<0b000, "add.f", addc, i32lo16z, i32hi16>;
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defm SUB_F_ : ALUarith<0b010, "sub.f", subc, i32lo16z, i32hi16>;
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}
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def : Pat<(addc GPR:$Rs1, i32lo16z:$imm),
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@ -366,8 +368,8 @@ def : Pat<(subc GPR:$Rs1, i32hi16:$imm),
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// Carry using addition and subtraction
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let F = 0, Uses = [SR] in {
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defm ADDC_ : ALUarith<0b001, "addc", adde, i32lo16s, i32hi16>;
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defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16s, i32hi16>;
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defm ADDC_ : ALUarith<0b001, "addc", adde, i32lo16z, i32hi16>;
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defm SUBB_ : ALUarith<0b011, "subb", sube, i32lo16z, i32hi16>;
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}
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def : Pat<(adde GPR:$Rs1, i32lo16z:$imm),
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@ -384,15 +386,27 @@ def : Pat<(sube GPR:$Rs1, i32hi16:$imm),
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// Flag setting ALU operations
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let isAsCheapAsAMove = 1, F = 1, Defs = [SR] in {
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defm ADDC_F_ : ALUarith<0b001, "addc.f", adde, i32lo16s, i32hi16>;
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defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16s, i32hi16>;
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let isCommutable = 1 in {
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defm AND_F_ : ALUlogic<0b100, "and.f", and, i32lo16and, i32hi16and>;
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defm OR_F_ : ALUlogic<0b101, "or.f", or, i32lo16z, i32hi16>;
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defm XOR_F_ : ALUlogic<0b110, "xor.f", xor, i32lo16s, i32hi16>;
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defm XOR_F_ : ALUlogic<0b110, "xor.f", xor, i32lo16z, i32hi16>;
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}
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}
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let isAsCheapAsAMove = 1, F = 1, Defs = [SR], Uses = [SR] in {
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defm ADDC_F_ : ALUarith<0b001, "addc.f", adde, i32lo16z, i32hi16>;
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defm SUBB_F_ : ALUarith<0b011, "subb.f", sube, i32lo16z, i32hi16>;
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}
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def : Pat<(LanaiSubbF GPR:$Rs1, GPR:$Rs2),
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(SUBB_F_R GPR:$Rs1, GPR:$Rs2)>;
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def : Pat<(LanaiSubbF GPR:$Rs1, i32lo16z:$imm),
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(SUBB_F_I_LO GPR:$Rs1, i32lo16z:$imm)>;
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def : Pat<(LanaiSubbF GPR:$Rs1, i32hi16:$imm),
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(SUBB_F_I_HI GPR:$Rs1, i32hi16:$imm)>;
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def : InstAlias<"mov $src, $dst", (ADD_R GPR:$dst, GPR:$src, R0)>;
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let isAsCheapAsAMove = 1, Rs1 = R0.Num, isCodeGenOnly = 1, H = 1, F = 0,
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@ -401,7 +415,7 @@ let isAsCheapAsAMove = 1, Rs1 = R0.Num, isCodeGenOnly = 1, H = 1, F = 0,
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"mov\t$imm16, $Rd",
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[(set GPR:$Rd, i32hi16:$imm16)]>;
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def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16s:$imm16)>;
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def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>;
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def : InstAlias<"mov $imm16, $dst", (ADD_I_HI GPR:$dst, R0, i32hi16:$imm16)>;
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def : InstAlias<"mov $imm16, $dst",
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(AND_I_LO GPR:$dst, R1, i32lo16and:$imm16)>;
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@ -693,9 +707,9 @@ multiclass SF<bits<3> op2Val, string AsmStr> {
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!strconcat(AsmStr, "\t$Rs1, $Rs2, %r0"),
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[(LanaiSetFlag (i32 GPR:$Rs1), (i32 GPR:$Rs2))]>;
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let F = 1, Rd = R0.Num, H = 0, Defs = [SR] in
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def _RI : InstRI<op2Val, (outs), (ins GPR:$Rs1, i32lo16s:$imm16),
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def _RI : InstRI<op2Val, (outs), (ins GPR:$Rs1, i32lo16z:$imm16),
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!strconcat(AsmStr, "\t$Rs1, $imm16, %r0"),
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[(LanaiSetFlag (i32 GPR:$Rs1), i32lo16s:$imm16)]>;
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[(LanaiSetFlag (i32 GPR:$Rs1), i32lo16z:$imm16)]>;
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}
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let isCodeGenOnly = 1 in {
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defm SFSUB_F : SF<0b010, "sub.f">;
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@ -820,9 +834,6 @@ let isCodeGenOnly = 1 in
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// Non-Instruction Patterns
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//===----------------------------------------------------------------------===//
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// signed 16-bit immediate
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def : Pat<(i32 i32lo16s:$imm), (MOVHI imm:$imm)>;
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// i32 0 and R0 can be used interchangeably.
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def : Pat<(i32 0), (i32 R0)>;
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// i32 -1 and R1 can be used interchangeably.
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@ -0,0 +1,108 @@
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; RUN: llc < %s | FileCheck %s
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; Test that basic 64-bit integer comparison operations assemble as expected.
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target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
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target triple = "lanai"
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; CHECK-LABEL: eq_i64:
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; CHECK: xor
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; CHECK: xor
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; CHECK: or.f
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; CHECK-NEXT: seq
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define i32 @eq_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp eq i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ne_i64:
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; CHECK: xor
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; CHECK: xor
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; CHECK: or.f
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; CHECK-NEXT: sne
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define i32 @ne_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp ne i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: slt_i64:
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; CHECK: sub.f %r7, %r19, %r3
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; CHECK: subb.f %r6, %r18, %r3
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; CHECK-NEXT: slt
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define i32 @slt_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp slt i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: sle_i64:
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; CHECK: sub.f %r19, %r7, %r3
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; CHECK: subb.f %r18, %r6, %r3
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; CHECK-NEXT: sge %rv
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define i32 @sle_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp sle i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ult_i64:
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; CHECK: sub.f %r7, %r19, %r3
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; CHECK: subb.f %r6, %r18, %r3
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; CHECK-NEXT: sult %rv
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define i32 @ult_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp ult i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: ule_i64:
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; CHECK: sub.f %r19, %r7, %r3
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; CHECK: subb.f %r18, %r6, %r3
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; CHECK-NEXT: suge %rv
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define i32 @ule_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp ule i64 %x, %y
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%b = zext i1 %a to i32
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ret i32 %b
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}
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; CHECK-LABEL: sgt_i64:
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; CHECK: sub.f %r19, %r7, %r3
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; CHECK: subb.f %r18, %r6, %r3
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; CHECK-NEXT: slt %rv
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define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) {
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%a = icmp sgt i64 %x, %y
|
||||
%b = zext i1 %a to i32
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sge_i64:
|
||||
; CHECK: sub.f %r7, %r19, %r3
|
||||
; CHECK: subb.f %r6, %r18, %r3
|
||||
; CHECK-NEXT: sge %rv
|
||||
define i32 @sge_i64(i64 inreg %x, i64 inreg %y) {
|
||||
%a = icmp sge i64 %x, %y
|
||||
%b = zext i1 %a to i32
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: ugt_i64:
|
||||
; CHECK: sub.f %r19, %r7, %r3
|
||||
; CHECK: subb.f %r18, %r6, %r3
|
||||
; CHECK-NEXT: sult %rv
|
||||
define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) {
|
||||
%a = icmp ugt i64 %x, %y
|
||||
%b = zext i1 %a to i32
|
||||
ret i32 %b
|
||||
}
|
||||
|
||||
; CHECK-LABEL: uge_i64:
|
||||
; CHECK: sub.f %r7, %r19, %r3
|
||||
; CHECK: subb.f %r6, %r18, %r3
|
||||
; CHECK-NEXT: suge %rv
|
||||
define i32 @uge_i64(i64 inreg %x, i64 inreg %y) {
|
||||
%a = icmp uge i64 %x, %y
|
||||
%b = zext i1 %a to i32
|
||||
ret i32 %b
|
||||
}
|
||||
|
|
@ -8,7 +8,7 @@ target triple = "lanai"
|
|||
; CHECK-LABEL: select_i32_bool:
|
||||
; CHECK: sub.f %r6, 0x0, %r0
|
||||
; CHECK: sel.ne %r7, %r18, %rv
|
||||
define i32 @select_i32_bool(i1 inreg %a, i32 inreg %b, i32 inreg %c) {
|
||||
define i32 @select_i32_bool(i1 zeroext inreg %a, i32 inreg %b, i32 inreg %c) {
|
||||
%cond = select i1 %a, i32 %b, i32 %c
|
||||
ret i32 %cond
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue