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AMDGPU/GlobalISel: Try generated matcher with intrinsics 

llvm-svn: 364933
This commit is contained in:
Matt Arsenault 2019-07-02 14:52:16 +00:00
parent a8bff4b963
commit 50be3481d4
3 changed files with 100 additions and 8 deletions
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15
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -375,18 +375,17 @@ bool AMDGPUInstructionSelector::selectG_INSERT(MachineInstr &I) const {
return true;
}
bool AMDGPUInstructionSelector::selectG_INTRINSIC(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
bool AMDGPUInstructionSelector::selectG_INTRINSIC(
MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
unsigned IntrinsicID = I.getOperand(I.getNumExplicitDefs()).getIntrinsicID();
switch (IntrinsicID) {
default:
break;
case Intrinsic::maxnum:
case Intrinsic::minnum:
case Intrinsic::amdgcn_cvt_pkrtz:
return selectImpl(I, CoverageInfo);
default:
return selectImpl(I, CoverageInfo);
}
return false;
}
static int getV_CMPOpcode(CmpInst::Predicate P, unsigned Size) {
@ -525,8 +524,7 @@ buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt,
}
bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &I,
CodeGenCoverage &CoverageInfo) const {
MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
MachineBasicBlock *BB = I.getParent();
MachineFunction *MF = BB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
@ -565,8 +563,9 @@ bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
I.eraseFromParent();
return constrainSelectedInstRegOperands(*Exp, TII, TRI, RBI);
}
default:
return selectImpl(I, CoverageInfo);
}
return false;
}
bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {

74
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir Normal file
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@ -0,0 +1,74 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# FIXME: Need to deal with constant bus restriction
# ---
# name: mbcnt_lo_ss
# legalized: true
# regBankSelected: true
# body: |
# bb.0:
# liveins: $sgpr0, $sgpr1
# %0:sgpr(s32) = COPY $sgpr0
# %1:sgpr(s32) = COPY $sgpr1
# %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
# S_ENDPGM 0, implicit %2
# ...
---
name: mbcnt_lo_sv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: mbcnt_lo_sv
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: smin_s32_vs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; GCN-LABEL: name: smin_s32_vs
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: smin_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GCN-LABEL: name: smin_s32_vv
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GCN: [[V_MBCNT_LO_U32_B32_e64_:%[0-9]+]]:vgpr_32 = V_MBCNT_LO_U32_B32_e64 [[COPY]], [[COPY1]], implicit $exec
; GCN: S_ENDPGM 0, implicit [[V_MBCNT_LO_U32_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %0, %1
S_ENDPGM 0, implicit %2
...

19
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir Normal file
View File

@ -0,0 +1,19 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefix=GCN
---
name: s_barrier
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: s_barrier
; GCN: S_BARRIER
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.s.barrier)
...