forked from OSchip/llvm-project
[DAGCombiner][x86] scalarize splatted vector FP ops
There are a variety of vector patterns that may be profitably reduced to a scalar op when scalar ops are performed using a subset (typically, the first lane) of the vector register file. For x86, this is true for float/double ops and element 0 because insert/extract is just a sub-register rename. Other targets should likely enable the hook in a similar way. Differential Revision: https://reviews.llvm.org/D60150 llvm-svn: 357760
This commit is contained in:
Sanjay Patel
parent
2b2f35a4e9
commit
50a8652785
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@ -2441,6 +2441,14 @@ public:
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return false;
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}
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/// Return true if extraction of a scalar element from the given vector type
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/// at the given index is cheap. For example, if scalar operations occur on
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/// the same register file as vector operations, then an extract element may
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/// be a sub-register rename rather than an actual instruction.
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virtual bool isExtractVecEltCheap(EVT VT, unsigned Index) const {
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return false;
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}
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/// Try to convert math with an overflow comparison into the corresponding DAG
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/// node operation. Targets may want to override this independently of whether
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/// the operation is legal/custom for the given type because it may obscure
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@ -18078,11 +18078,28 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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// If it is a splat, check if the argument vector is another splat or a
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// build_vector.
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if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
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SDNode *V = N0.getNode();
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int SplatIndex = SVN->getSplatIndex();
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if (TLI.isExtractVecEltCheap(VT, SplatIndex) &&
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ISD::isBinaryOp(N0.getNode())) {
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// splat (vector_bo L, R), Index -->
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// splat (scalar_bo (extelt L, Index), (extelt R, Index))
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SDValue L = N0.getOperand(0), R = N0.getOperand(1);
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SDLoc DL(N);
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EVT EltVT = VT.getScalarType();
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SDValue Index = DAG.getIntPtrConstant(SplatIndex, DL);
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SDValue ExtL = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, L, Index);
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SDValue ExtR = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, R, Index);
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SDValue NewBO = DAG.getNode(N0.getOpcode(), DL, EltVT, ExtL, ExtR,
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N0.getNode()->getFlags());
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SDValue Insert = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, NewBO);
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SmallVector<int, 16> ZeroMask(VT.getVectorNumElements(), 0);
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return DAG.getVectorShuffle(VT, DL, Insert, DAG.getUNDEF(VT), ZeroMask);
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}
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// If this is a bit convert that changes the element type of the vector but
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// not the number of vector elements, look through it. Be careful not to
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// look though conversions that change things like v4f32 to v2f64.
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SDNode *V = N0.getNode();
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if (V->getOpcode() == ISD::BITCAST) {
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SDValue ConvInput = V->getOperand(0);
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if (ConvInput.getValueType().isVector() &&
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@ -18115,7 +18132,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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return N0;
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// Canonicalize any other splat as a build_vector.
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const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
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SDValue Splatted = V->getOperand(SplatIndex);
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SmallVector<SDValue, 8> Ops(NumElts, Splatted);
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SDValue NewBV = DAG.getBuildVector(V->getValueType(0), SDLoc(N), Ops);
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@ -1074,6 +1074,12 @@ namespace llvm {
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/// supported.
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bool shouldScalarizeBinop(SDValue) const override;
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/// Extract of a scalar FP value from index 0 of a vector is free.
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bool isExtractVecEltCheap(EVT VT, unsigned Index) const override {
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EVT EltVT = VT.getScalarType();
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return (EltVT == MVT::f32 || EltVT == MVT::f64) && Index == 0;
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}
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/// Overflow nodes should get combined/lowered to optimal instructions
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/// (they should allow eliminating explicit compares by getting flags from
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/// math ops).
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@ -274,7 +274,7 @@ define <2 x double> @hadd_v2f64(<2 x double> %a) {
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movapd %xmm0, %xmm1
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
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; SSSE3_SLOW-NEXT: addpd %xmm0, %xmm1
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; SSSE3_SLOW-NEXT: addsd %xmm0, %xmm1
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm1[0,0]
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; SSSE3_SLOW-NEXT: retq
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;
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@ -286,7 +286,7 @@ define <2 x double> @hadd_v2f64(<2 x double> %a) {
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; AVX1_SLOW-LABEL: hadd_v2f64:
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; AVX1_SLOW: # %bb.0:
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; AVX1_SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; AVX1_SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; AVX1_SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX1_SLOW-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX1_SLOW-NEXT: retq
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;
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@ -298,7 +298,7 @@ define <2 x double> @hadd_v2f64(<2 x double> %a) {
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; AVX2_SLOW-LABEL: hadd_v2f64:
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; AVX2_SLOW: # %bb.0:
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; AVX2_SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; AVX2_SLOW-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; AVX2_SLOW-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX2_SLOW-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX2_SLOW-NEXT: retq
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;
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@ -398,12 +398,12 @@ define <4 x double> @hadd_v4f64(<4 x double> %a) {
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movapd %xmm0, %xmm2
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
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; SSSE3_SLOW-NEXT: movapd %xmm1, %xmm3
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
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; SSSE3_SLOW-NEXT: addpd %xmm1, %xmm3
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; SSSE3_SLOW-NEXT: addpd %xmm0, %xmm2
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; SSSE3_SLOW-NEXT: addsd %xmm0, %xmm2
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm2[0,0]
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm3[0,0]
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; SSSE3_SLOW-NEXT: movapd %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
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; SSSE3_SLOW-NEXT: addsd %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm2[0,0]
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; SSSE3_SLOW-NEXT: retq
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;
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; SSSE3_FAST-LABEL: hadd_v4f64:
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@ -447,7 +447,7 @@ define <2 x double> @hsub_v2f64(<2 x double> %a) {
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movapd %xmm0, %xmm1
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
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; SSSE3_SLOW-NEXT: subpd %xmm1, %xmm0
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; SSSE3_SLOW-NEXT: subsd %xmm1, %xmm0
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3_SLOW-NEXT: retq
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;
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@ -459,7 +459,7 @@ define <2 x double> @hsub_v2f64(<2 x double> %a) {
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; AVX1_SLOW-LABEL: hsub_v2f64:
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; AVX1_SLOW: # %bb.0:
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; AVX1_SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; AVX1_SLOW-NEXT: vsubpd %xmm1, %xmm0, %xmm0
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; AVX1_SLOW-NEXT: vsubsd %xmm1, %xmm0, %xmm0
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; AVX1_SLOW-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX1_SLOW-NEXT: retq
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;
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@ -471,7 +471,7 @@ define <2 x double> @hsub_v2f64(<2 x double> %a) {
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; AVX2_SLOW-LABEL: hsub_v2f64:
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; AVX2_SLOW: # %bb.0:
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; AVX2_SLOW-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
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; AVX2_SLOW-NEXT: vsubpd %xmm1, %xmm0, %xmm0
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; AVX2_SLOW-NEXT: vsubsd %xmm1, %xmm0, %xmm0
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; AVX2_SLOW-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX2_SLOW-NEXT: retq
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;
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@ -491,11 +491,11 @@ define <4 x double> @hsub_v4f64(<4 x double> %a) {
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; SSSE3_SLOW: # %bb.0:
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; SSSE3_SLOW-NEXT: movapd %xmm0, %xmm2
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
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; SSSE3_SLOW-NEXT: movapd %xmm1, %xmm3
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm3 = xmm3[1],xmm1[1]
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; SSSE3_SLOW-NEXT: subpd %xmm3, %xmm1
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; SSSE3_SLOW-NEXT: subpd %xmm2, %xmm0
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; SSSE3_SLOW-NEXT: subsd %xmm2, %xmm0
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0]
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; SSSE3_SLOW-NEXT: movapd %xmm1, %xmm2
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; SSSE3_SLOW-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm1[1]
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; SSSE3_SLOW-NEXT: subsd %xmm2, %xmm1
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; SSSE3_SLOW-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]
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; SSSE3_SLOW-NEXT: retq
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;
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@ -379,13 +379,13 @@ define <4 x double> @load_fdiv_op0_constant_v4f64(double* %p) nounwind {
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define <2 x double> @fadd_splat_splat_v2f64(<2 x double> %vx, <2 x double> %vy) {
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; SSE-LABEL: fadd_splat_splat_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: addpd %xmm1, %xmm0
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; SSE-NEXT: addsd %xmm1, %xmm0
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; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fadd_splat_splat_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%splatx = shufflevector <2 x double> %vx, <2 x double> undef, <2 x i32> zeroinitializer
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@ -397,14 +397,14 @@ define <2 x double> @fadd_splat_splat_v2f64(<2 x double> %vx, <2 x double> %vy)
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define <4 x double> @fsub_splat_splat_v4f64(double %x, double %y) {
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; SSE-LABEL: fsub_splat_splat_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: subpd %xmm1, %xmm0
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; SSE-NEXT: subsd %xmm1, %xmm0
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; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
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; SSE-NEXT: movapd %xmm0, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsub_splat_splat_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vsubpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX-NEXT: retq
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@ -419,13 +419,13 @@ define <4 x double> @fsub_splat_splat_v4f64(double %x, double %y) {
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define <4 x float> @fmul_splat_splat_v4f32(<4 x float> %vx, <4 x float> %vy) {
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; SSE-LABEL: fmul_splat_splat_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: mulps %xmm1, %xmm0
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; SSE-NEXT: mulss %xmm1, %xmm0
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fmul_splat_splat_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; AVX-NEXT: retq
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%splatx = shufflevector <4 x float> %vx, <4 x float> undef, <4 x i32> zeroinitializer
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@ -437,26 +437,14 @@ define <4 x float> @fmul_splat_splat_v4f32(<4 x float> %vx, <4 x float> %vy) {
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define <8 x float> @fdiv_splat_splat_v8f32(<8 x float> %vx, <8 x float> %vy) {
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; SSE-LABEL: fdiv_splat_splat_v8f32:
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; SSE: # %bb.0:
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; SSE-NEXT: rcpps %xmm2, %xmm3
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; SSE-NEXT: mulps %xmm3, %xmm2
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; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; SSE-NEXT: subps %xmm2, %xmm1
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; SSE-NEXT: mulps %xmm3, %xmm1
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; SSE-NEXT: addps %xmm3, %xmm1
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; SSE-NEXT: mulps %xmm0, %xmm1
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; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
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; SSE-NEXT: movaps %xmm1, %xmm0
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; SSE-NEXT: divss %xmm2, %xmm0
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; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; SSE-NEXT: movaps %xmm0, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fdiv_splat_splat_v8f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vrcpps %ymm1, %ymm2
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; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm1
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; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
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; AVX-NEXT: vsubps %xmm1, %xmm3, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vaddps %xmm1, %xmm2, %xmm1
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX-NEXT: retq
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@ -569,7 +557,7 @@ define <4 x double> @fsub_const_op0_splat_v4f64(double %x) {
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; SSE-LABEL: fsub_const_op0_splat_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE-NEXT: subpd %xmm0, %xmm1
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; SSE-NEXT: subsd %xmm0, %xmm1
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; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
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; SSE-NEXT: movapd %xmm1, %xmm0
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; SSE-NEXT: retq
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@ -577,7 +565,7 @@ define <4 x double> @fsub_const_op0_splat_v4f64(double %x) {
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; AVX-LABEL: fsub_const_op0_splat_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vsubpd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
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; AVX-NEXT: retq
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@ -667,13 +655,13 @@ define <8 x float> @fdiv_const_op1_splat_v8f32(<8 x float> %vx) {
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define <2 x double> @splat0_fadd_v2f64(<2 x double> %vx, <2 x double> %vy) {
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; SSE-LABEL: splat0_fadd_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: addpd %xmm1, %xmm0
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; SSE-NEXT: addsd %xmm1, %xmm0
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; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
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; SSE-NEXT: retq
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;
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; AVX-LABEL: splat0_fadd_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
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; AVX-NEXT: retq
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%b = fadd <2 x double> %vx, %vy
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@ -684,14 +672,14 @@ define <2 x double> @splat0_fadd_v2f64(<2 x double> %vx, <2 x double> %vy) {
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define <4 x double> @splat0_fsub_v4f64(double %x, double %y) {
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; SSE-LABEL: splat0_fsub_v4f64:
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; SSE: # %bb.0:
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; SSE-NEXT: subpd %xmm1, %xmm0
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; SSE-NEXT: subsd %xmm1, %xmm0
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; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
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; SSE-NEXT: movapd %xmm0, %xmm1
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; SSE-NEXT: retq
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;
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; AVX-LABEL: splat0_fsub_v4f64:
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; AVX: # %bb.0:
|
||||
; AVX-NEXT: vsubpd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vsubsd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX-NEXT: retq
|
||||
|
|
@ -705,13 +693,13 @@ define <4 x double> @splat0_fsub_v4f64(double %x, double %y) {
|
|||
define <4 x float> @splat0_fmul_v4f32(<4 x float> %vx, <4 x float> %vy) {
|
||||
; SSE-LABEL: splat0_fmul_v4f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: mulps %xmm1, %xmm0
|
||||
; SSE-NEXT: mulss %xmm1, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splat0_fmul_v4f32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX-NEXT: retq
|
||||
%b = fmul fast <4 x float> %vx, %vy
|
||||
|
|
@ -722,26 +710,14 @@ define <4 x float> @splat0_fmul_v4f32(<4 x float> %vx, <4 x float> %vy) {
|
|||
define <8 x float> @splat0_fdiv_v8f32(<8 x float> %vx, <8 x float> %vy) {
|
||||
; SSE-LABEL: splat0_fdiv_v8f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: rcpps %xmm2, %xmm3
|
||||
; SSE-NEXT: mulps %xmm3, %xmm2
|
||||
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
||||
; SSE-NEXT: subps %xmm2, %xmm1
|
||||
; SSE-NEXT: mulps %xmm3, %xmm1
|
||||
; SSE-NEXT: addps %xmm3, %xmm1
|
||||
; SSE-NEXT: mulps %xmm0, %xmm1
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: divss %xmm2, %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; SSE-NEXT: movaps %xmm0, %xmm1
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splat0_fdiv_v8f32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vrcpps %ymm1, %ymm2
|
||||
; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm1
|
||||
; AVX-NEXT: vmovaps {{.*#+}} xmm3 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
||||
; AVX-NEXT: vsubps %xmm1, %xmm3, %xmm1
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm2, %xmm1
|
||||
; AVX-NEXT: vaddps %xmm1, %xmm2, %xmm1
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX-NEXT: retq
|
||||
|
|
@ -753,16 +729,13 @@ define <8 x float> @splat0_fdiv_v8f32(<8 x float> %vx, <8 x float> %vy) {
|
|||
define <2 x double> @splat0_fadd_const_op1_v2f64(<2 x double> %vx) {
|
||||
; SSE-LABEL: splat0_fadd_const_op1_v2f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE-NEXT: addpd %xmm0, %xmm1
|
||||
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
|
||||
; SSE-NEXT: movapd %xmm1, %xmm0
|
||||
; SSE-NEXT: addsd {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splat0_fadd_const_op1_v2f64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vaddsd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; AVX-NEXT: retq
|
||||
%b = fadd <2 x double> %vx, <double 42.0, double 12.0>
|
||||
|
|
@ -774,7 +747,7 @@ define <4 x double> @splat0_fsub_const_op0_v4f64(double %x) {
|
|||
; SSE-LABEL: splat0_fsub_const_op0_v4f64:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; SSE-NEXT: subpd %xmm0, %xmm1
|
||||
; SSE-NEXT: subsd %xmm0, %xmm1
|
||||
; SSE-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0,0]
|
||||
; SSE-NEXT: movapd %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
|
|
@ -782,7 +755,7 @@ define <4 x double> @splat0_fsub_const_op0_v4f64(double %x) {
|
|||
; AVX-LABEL: splat0_fsub_const_op0_v4f64:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
|
||||
; AVX-NEXT: vsubpd %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vsubsd %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0]
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX-NEXT: retq
|
||||
|
|
@ -795,16 +768,13 @@ define <4 x double> @splat0_fsub_const_op0_v4f64(double %x) {
|
|||
define <4 x float> @splat0_fmul_const_op1_v4f32(<4 x float> %vx) {
|
||||
; SSE-LABEL: splat0_fmul_const_op1_v4f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSE-NEXT: mulps %xmm0, %xmm1
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: mulss {{.*}}(%rip), %xmm0
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splat0_fmul_const_op1_v4f32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm0
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX-NEXT: retq
|
||||
%b = fmul fast <4 x float> %vx, <float 6.0, float -1.0, float 1.0, float 7.0>
|
||||
|
|
@ -821,13 +791,6 @@ define <8 x float> @splat0_fdiv_const_op1_v8f32(<8 x float> %vx) {
|
|||
;
|
||||
; AVX-LABEL: splat0_fdiv_const_op1_v8f32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; AVX-NEXT: vrcpps %ymm1, %ymm1
|
||||
; AVX-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
||||
; AVX-NEXT: vsubps %xmm1, %xmm2, %xmm2
|
||||
; AVX-NEXT: vmulps %xmm2, %xmm1, %xmm2
|
||||
; AVX-NEXT: vaddps %xmm2, %xmm1, %xmm1
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX-NEXT: retq
|
||||
|
|
@ -839,24 +802,16 @@ define <8 x float> @splat0_fdiv_const_op1_v8f32(<8 x float> %vx) {
|
|||
define <8 x float> @splat0_fdiv_const_op0_v8f32(<8 x float> %vx) {
|
||||
; SSE-LABEL: splat0_fdiv_const_op0_v8f32:
|
||||
; SSE: # %bb.0:
|
||||
; SSE-NEXT: rcpps %xmm0, %xmm2
|
||||
; SSE-NEXT: mulps %xmm2, %xmm0
|
||||
; SSE-NEXT: movaps {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
||||
; SSE-NEXT: subps %xmm0, %xmm1
|
||||
; SSE-NEXT: mulps %xmm2, %xmm1
|
||||
; SSE-NEXT: addps %xmm2, %xmm1
|
||||
; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; SSE-NEXT: divss %xmm0, %xmm1
|
||||
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
||||
; SSE-NEXT: movaps %xmm1, %xmm0
|
||||
; SSE-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splat0_fdiv_const_op0_v8f32:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vrcpps %ymm0, %ymm1
|
||||
; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vmovaps {{.*#+}} xmm2 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0,1.0E+0]
|
||||
; AVX-NEXT: vsubps %xmm0, %xmm2, %xmm0
|
||||
; AVX-NEXT: vmulps %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vaddps %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
||||
; AVX-NEXT: vdivss %xmm0, %xmm1, %xmm0
|
||||
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,0,0]
|
||||
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
||||
; AVX-NEXT: retq
|
||||
|
|
|
|||
Loading…
Reference in New Issue