forked from OSchip/llvm-project
[mips] divide macro instruction cleanup.
Clean up the implementation of divide macro expansion by getting rid of a FIXME regarding magic numbers and branch instructions. Match GAS' behaviour for expansion of ddiv / div in the two and three operand cases. Add the two operand alias for MIPSR6. Finally, optimize macro expansion cases where the divisior is the $zero register. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D29887 llvm-svn: 294960
This commit is contained in:
Simon Dardis
parent
fd6a84fbaa
commit
509da1a46d
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@ -968,6 +968,16 @@ public:
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/// Render the operand to an MCInst as a GPR32
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/// Asserts if the wrong number of operands are requested, or the operand
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/// is not a k_RegisterIndex compatible with RegKind_GPR
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void addGPR32ZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
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}
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void addGPR32NonZeroAsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
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}
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void addGPR32AsmRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getGPR32Reg()));
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@ -1524,6 +1534,15 @@ public:
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return Op;
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}
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bool isGPRZeroAsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index == 0;
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}
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bool isGPRNonZeroAsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index > 0 &&
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RegIdx.Index <= 31;
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}
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bool isGPRAsmReg() const {
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return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31;
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}
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@ -1883,6 +1902,61 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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}
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}
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// Warn on division by zero. We're checking here as all instructions get
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// processed here, not just the macros that need expansion.
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//
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// The MIPS backend models most of the divison instructions and macros as
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// three operand instructions. The pre-R6 divide instructions however have
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// two operands and explicitly define HI/LO as part of the instruction,
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// not in the operands.
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unsigned FirstOp = 1;
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unsigned SecondOp = 2;
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switch (Inst.getOpcode()) {
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default:
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break;
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case Mips::SDivIMacro:
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case Mips::UDivIMacro:
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case Mips::DSDivIMacro:
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case Mips::DUDivIMacro:
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if (Inst.getOperand(2).getImm() == 0) {
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if (Inst.getOperand(1).getReg() == Mips::ZERO ||
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Inst.getOperand(1).getReg() == Mips::ZERO_64)
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Warning(IDLoc, "dividing zero by zero");
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else
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Warning(IDLoc, "division by zero");
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}
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break;
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case Mips::DSDIV:
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case Mips::SDIV:
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case Mips::UDIV:
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case Mips::DUDIV:
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case Mips::UDIV_MM:
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case Mips::SDIV_MM:
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FirstOp = 0;
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SecondOp = 1;
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case Mips::SDivMacro:
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case Mips::DSDivMacro:
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case Mips::UDivMacro:
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case Mips::DUDivMacro:
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case Mips::DIV:
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case Mips::DIVU:
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case Mips::DDIV:
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case Mips::DDIVU:
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case Mips::DIVU_MMR6:
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case Mips::DDIVU_MM64R6:
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case Mips::DIV_MMR6:
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case Mips::DDIV_MM64R6:
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if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
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Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
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if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
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Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
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Warning(IDLoc, "dividing zero by zero");
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else
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Warning(IDLoc, "division by zero");
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}
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break;
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}
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// For PIC code convert unconditional jump to unconditional branch.
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if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
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inPicMode()) {
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@ -3360,6 +3434,14 @@ bool MipsAsmParser::expandCondBranches(MCInst &Inst, SMLoc IDLoc,
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return false;
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}
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// Expand a integer division macro.
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//
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// Notably we don't have to emit a warning when encountering $rt as the $zero
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// register, or 0 as an immediate. processInstruction() has already done that.
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//
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// The destination register can only be $zero when expanding (S)DivIMacro or
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// D(S)DivMacro.
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bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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const MCSubtargetInfo *STI, const bool IsMips64,
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const bool Signed) {
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@ -3408,10 +3490,6 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return true;
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if (ImmValue == 0) {
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if (RsReg == Mips::ZERO || RsReg == Mips::ZERO_64)
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Warning(IDLoc, "dividing zero by zero");
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else
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Warning(IDLoc, "division by zero");
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if (UseTraps)
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TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
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else
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@ -3420,10 +3498,10 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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}
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if (ImmValue == 1) {
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TOut.emitRRR(Mips::ADDu, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
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TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
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return false;
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} else if (Signed && ImmValue == -1) {
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TOut.emitRRR(SubOp, RdReg, Mips::ZERO, RsReg, IDLoc, STI);
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TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI);
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return false;
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} else {
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if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
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@ -3436,51 +3514,31 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return true;
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}
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if (RsReg == Mips::ZERO || RsReg == Mips::ZERO_64) {
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if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)
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Warning(IDLoc, "dividing zero by zero");
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if (IsMips64) {
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if (Signed && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
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if (UseTraps) {
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TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
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return false;
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}
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TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
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return false;
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}
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} else {
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TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
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return false;
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}
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}
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// If the macro expansion of (d)div(u) would always trap or break, insert
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// the trap/break and exit. This gives a different result to GAS. GAS has
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// an inconsistency/missed optimization in that not all cases are handled
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// equivalently. As the observed behaviour is the same, we're ok.
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if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
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Warning(IDLoc, "division by zero");
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if (Signed) {
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if (UseTraps) {
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TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
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return false;
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}
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TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
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if (UseTraps) {
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TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
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return false;
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}
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TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
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return false;
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}
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// FIXME: The values for these two BranchTarget variables may be different in
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// micromips. These magic numbers need to be removed.
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unsigned BranchTargetNoTraps;
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unsigned BranchTarget;
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// Temporary label for first branch traget
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MCContext &Context = TOut.getStreamer().getContext();
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MCSymbol *BrTarget;
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MCOperand LabelOp;
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if (UseTraps) {
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BranchTarget = IsMips64 ? 12 : 8;
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TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
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} else {
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BranchTarget = IsMips64 ? 20 : 16;
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BranchTargetNoTraps = 8;
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// Branch to the li instruction.
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TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI);
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BrTarget = Context.createTempSymbol();
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LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
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TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
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}
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TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
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@ -3489,6 +3547,9 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
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if (!Signed) {
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if (!UseTraps)
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TOut.getStreamer().EmitLabel(BrTarget);
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TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
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return false;
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}
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@ -3497,15 +3558,23 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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if (!ATReg)
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return true;
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if (!UseTraps)
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TOut.getStreamer().EmitLabel(BrTarget);
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TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
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// Temporary label for the second branch target.
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MCSymbol *BrTargetEnd = Context.createTempSymbol();
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MCOperand LabelOpEnd =
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MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));
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// Branch to the mflo instruction.
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TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
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if (IsMips64) {
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// Branch to the mflo instruction.
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TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
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TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
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TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI);
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} else {
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// Branch to the mflo instruction.
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TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
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TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
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}
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@ -3513,10 +3582,12 @@ bool MipsAsmParser::expandDiv(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
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else {
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// Branch to the mflo instruction.
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TOut.emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, STI);
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TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
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TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
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TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
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}
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TOut.getStreamer().EmitLabel(BrTargetEnd);
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TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
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return false;
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}
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@ -917,6 +917,12 @@ def : MipsInstAlias<"jrc $rs", (JIC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"jalrc $rs", (JIALC GPR32Opnd:$rs, 0), 1>, ISA_MIPS32R6, GPR_32;
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}
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def : MipsInstAlias<"div $rs, $rt", (DIV GPR32Opnd:$rs, GPR32Opnd:$rs,
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GPR32Opnd:$rt)>, ISA_MIPS32R6;
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def : MipsInstAlias<"divu $rs, $rt", (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs,
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GPR32Opnd:$rt)>, ISA_MIPS32R6;
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//===----------------------------------------------------------------------===//
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//
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// Patterns and Pseudo Instructions
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@ -835,3 +835,48 @@ def DMULMacro : MipsAsmPseudoInst<(outs), (ins GPR64Opnd:$rs, GPR64Opnd:$rt,
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"dmul\t$rs, $rt, $rd"> {
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let InsnPredicates = [HasMips3, NotMips64r6, NotCnMips];
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}
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let AdditionalPredicates = [NotInMicroMips] in {
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def DSDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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"ddiv\t$rd, $rs, $rt">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DSDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"ddiv\t$rd, $rs, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DUDivMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, GPR64Opnd:$rt),
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"ddivu\t$rd, $rs, $rt">,
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ISA_MIPS3_NOT_32R6_64R6;
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def DUDivIMacro : MipsAsmPseudoInst<(outs GPR64Opnd:$rd),
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(ins GPR64Opnd:$rs, imm64:$imm),
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"ddivu\t$rd, $rs, $imm">,
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ISA_MIPS3_NOT_32R6_64R6;
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// GAS expands 'div' and 'ddiv' differently when the destination
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// register is $zero and the instruction is in the two operand
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// form. 'ddiv' gets expanded, while 'div' is not expanded.
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def : MipsInstAlias<"ddiv $rs, $rt", (DSDivMacro GPR64Opnd:$rs,
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GPR64Opnd:$rs,
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GPR64Opnd:$rt), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR64Opnd:$rd,
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GPR64Opnd:$rd,
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imm64:$imm), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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// GAS expands 'divu' and 'ddivu' differently when the destination
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// register is $zero and the instruction is in the two operand
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// form. 'ddivu' gets expanded, while 'divu' is not expanded.
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def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR64Opnd:$rt,
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GPR64Opnd:$rt,
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GPR64Opnd:$rs), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR64Opnd:$rd,
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GPR64Opnd:$rd,
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imm64:$imm), 0>,
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ISA_MIPS3_NOT_32R6_64R6;
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}
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@ -2582,7 +2582,7 @@ def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
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// Once the tablegen-erated errors are made better, this needs to be fixed and
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// predicates needs to be restored.
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def SDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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def SDivMacro : MipsAsmPseudoInst<(outs GPR32NonZeroOpnd:$rd),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"div\t$rd, $rs, $rt">,
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ISA_MIPS1_NOT_32R6_64R6;
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@ -2598,46 +2598,30 @@ def UDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, simm32:$imm),
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"divu\t$rd, $rs, $imm">,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"div $rt, $rs", (SDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
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GPR32Opnd:$rs), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"div $rs, $rt", (SDIV GPR32ZeroOpnd:$rs,
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GPR32Opnd:$rt), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"div $rs, $rt", (SDivMacro GPR32NonZeroOpnd:$rs,
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GPR32NonZeroOpnd:$rs,
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GPR32Opnd:$rt), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"div $rd, $imm", (SDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
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simm32:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
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def : MipsInstAlias<"divu $rt, $rs", (UDIV GPR32ZeroOpnd:$rt,
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GPR32Opnd:$rs), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"divu $rt, $rs", (UDivMacro GPR32NonZeroOpnd:$rt,
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GPR32NonZeroOpnd:$rt,
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GPR32Opnd:$rs), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<"divu $rd, $imm", (UDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
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simm32:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def DSDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
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(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
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"ddiv\t$rd, $rs, $rt">,
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ISA_MIPS64_NOT_64R6;
|
||||
def DSDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
|
||||
(ins GPR32Opnd:$rs, imm64:$imm),
|
||||
"ddiv\t$rd, $rs, $imm">,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def DUDivMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
|
||||
(ins GPR32Opnd:$rs, GPR32Opnd:$rt),
|
||||
"ddivu\t$rd, $rs, $rt">,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def DUDivIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd),
|
||||
(ins GPR32Opnd:$rs, imm64:$imm),
|
||||
"ddivu\t$rd, $rs, $imm">,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def : MipsInstAlias<"ddiv $rt, $rs", (DSDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
|
||||
GPR32Opnd:$rs), 0>,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def : MipsInstAlias<"ddiv $rd, $imm", (DSDivIMacro GPR32Opnd:$rd, GPR32Opnd:$rd,
|
||||
imm64:$imm), 0>,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def : MipsInstAlias<"ddivu $rt, $rs", (DUDivMacro GPR32Opnd:$rt, GPR32Opnd:$rt,
|
||||
GPR32Opnd:$rs), 0>,
|
||||
ISA_MIPS64_NOT_64R6;
|
||||
def : MipsInstAlias<"ddivu $rd, $imm", (DUDivIMacro GPR32Opnd:$rd,
|
||||
GPR32Opnd:$rd, imm64:$imm),
|
||||
0>, ISA_MIPS64_NOT_64R6;
|
||||
|
||||
def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
|
||||
"ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
|
||||
|
|
|
|||
|
|
@ -290,6 +290,25 @@ class GPR32Class<list<ValueType> regTypes> :
|
|||
K0, K1, GP, SP, FP, RA)>;
|
||||
|
||||
def GPR32 : GPR32Class<[i32]>;
|
||||
|
||||
def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
|
||||
// Reserved
|
||||
ZERO)>;
|
||||
|
||||
def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add
|
||||
// Reserved
|
||||
AT,
|
||||
// Return Values and Arguments
|
||||
V0, V1, A0, A1, A2, A3,
|
||||
// Not preserved across procedure calls
|
||||
T0, T1, T2, T3, T4, T5, T6, T7,
|
||||
// Callee save
|
||||
S0, S1, S2, S3, S4, S5, S6, S7,
|
||||
// Not preserved across procedure calls
|
||||
T8, T9,
|
||||
// Reserved
|
||||
K0, K1, GP, SP, FP, RA)>;
|
||||
|
||||
def DSPR : GPR32Class<[v4i8, v2i16]>;
|
||||
|
||||
def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
|
||||
|
|
@ -317,7 +336,7 @@ def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
|
|||
S0, S2, S3, S4)>;
|
||||
|
||||
def GPR64 : RegisterClass<"Mips", [i64], 64, (add
|
||||
// Reserved
|
||||
// Reserved
|
||||
ZERO_64, AT_64,
|
||||
// Return Values and Arguments
|
||||
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
|
||||
|
|
@ -479,6 +498,16 @@ def GPR64AsmOperand : MipsAsmRegOperand {
|
|||
let PredicateMethod = "isGPRAsmReg";
|
||||
}
|
||||
|
||||
def GPR32ZeroAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "GPR32ZeroAsmReg";
|
||||
let PredicateMethod = "isGPRZeroAsmReg";
|
||||
}
|
||||
|
||||
def GPR32NonZeroAsmOperand : MipsAsmRegOperand {
|
||||
let Name = "GPR32NonZeroAsmReg";
|
||||
let PredicateMethod = "isGPRNonZeroAsmReg";
|
||||
}
|
||||
|
||||
def GPR32AsmOperand : MipsAsmRegOperand {
|
||||
let Name = "GPR32AsmReg";
|
||||
let PredicateMethod = "isGPRAsmReg";
|
||||
|
|
@ -550,6 +579,14 @@ def MSACtrlAsmOperand : MipsAsmRegOperand {
|
|||
let Name = "MSACtrlAsmReg";
|
||||
}
|
||||
|
||||
def GPR32ZeroOpnd : RegisterOperand<GPR32ZERO> {
|
||||
let ParserMatchClass = GPR32ZeroAsmOperand;
|
||||
}
|
||||
|
||||
def GPR32NonZeroOpnd : RegisterOperand<GPR32NONZERO> {
|
||||
let ParserMatchClass = GPR32NonZeroAsmOperand;
|
||||
}
|
||||
|
||||
def GPR32Opnd : RegisterOperand<GPR32> {
|
||||
let ParserMatchClass = GPR32AsmOperand;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,48 +1,64 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 | \
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | \
|
||||
# RUN: FileCheck %s --check-prefix=CHECK-NOTRAP
|
||||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 \
|
||||
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
|
||||
|
||||
ddiv $25,$11
|
||||
# CHECK-NOTRAP: bne $11, $zero, 8 # encoding: [0x15,0x60,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp0
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $11, $1, 20 # encoding: [0x15,0x61,0x00,0x05]
|
||||
# CHECK-NOTRAP: bne $11, $1, .Ltmp1 # encoding: [0x15,0x61,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-NOTRAP: bne $25, $1, 8 # encoding: [0x17,0x21,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $25, $1, .Ltmp1 # encoding: [0x17,0x21,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp1
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
|
||||
# CHECK-TRAP: ddiv $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1e]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $11, $1, 12 # encoding: [0x15,0x61,0x00,0x03]
|
||||
# CHECK-TRAP: bne $11, $1, .Ltmp0 # encoding: [0x15,0x61,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
|
||||
# CHECK-TRAP: .Ltmp0:
|
||||
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
ddiv $24,$12
|
||||
# CHECK-NOTRAP: bne $12, $zero, 8 # encoding: [0x15,0x80,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $12, $zero, .Ltmp2 # encoding: [0x15,0x80,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp2:
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $12, $1, 20 # encoding: [0x15,0x81,0x00,0x05]
|
||||
# CHECK-NOTRAP: bne $12, $1, .Ltmp3 # encoding: [0x15,0x81,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-NOTRAP: bne $24, $1, 8 # encoding: [0x17,0x01,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $24, $1, .Ltmp3 # encoding: [0x17,0x01,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp3
|
||||
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
|
||||
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
|
||||
# CHECK-TRAP: ddiv $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1e]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $12, $1, 12 # encoding: [0x15,0x81,0x00,0x03]
|
||||
# CHECK-TRAP: bne $12, $1, .Ltmp1 # encoding: [0x15,0x81,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
|
||||
# CHECK-TRAP: .Ltmp1:
|
||||
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
|
||||
ddiv $25,$0
|
||||
|
|
@ -50,24 +66,17 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
ddiv $0,$9
|
||||
# CHECK-NOTRAP: bne $9, $zero, 8 # encoding: [0x15,0x20,0x00,0x02]
|
||||
# CHECK-NOTRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $9, $1, 20 # encoding: [0x15,0x21,0x00,0x05]
|
||||
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-NOTRAP: bne $zero, $1, 8 # encoding: [0x14,0x01,0x00,0x02]
|
||||
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
|
||||
# CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
|
||||
# CHECK-TRAP: ddiv $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1e]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $9, $1, 12 # encoding: [0x15,0x21,0x00,0x03]
|
||||
# CHECK-TRAP: bne $9, $1, .Ltmp2 # encoding: [0x15,0x21,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-TRAP: teq $zero, $1, 6 # encoding: [0x00,0x01,0x01,0xb4]
|
||||
# CHECH-TRAP: .Ltmp2:
|
||||
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
|
||||
ddiv $0,$0
|
||||
|
|
@ -83,8 +92,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
ddiv $4,1
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
|
||||
ddiv $4,-1
|
||||
# CHECK-NOTRAP: dsub $4, $zero, $4 # encoding: [0x00,0x04,0x20,0x2e]
|
||||
|
|
@ -190,24 +199,32 @@
|
|||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddiv $4,$5,$6
|
||||
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $6, $zero, .Ltmp6 # encoding: [0x14,0xc0,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp6-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp6:
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $6, $1, 20 # encoding: [0x14,0xc1,0x00,0x05]
|
||||
# CHECK-NOTRAP: bne $6, $1, .Ltmp7 # encoding: [0x14,0xc1,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp7-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-NOTRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $5, $1, .Ltmp7 # encoding: [0x14,0xa1,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp7-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: sll $zero, $zero, 0 # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp7:
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
|
||||
# CHECK-TRAP: ddiv $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1e]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $6, $1, 12 # encoding: [0x14,0xc1,0x00,0x03]
|
||||
# CHECK-TRAP: bne $6, $1, .Ltmp3 # encoding: [0x14,0xc1,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: addiu $1, $zero, 1 # encoding: [0x24,0x01,0x00,0x01]
|
||||
# CHECK-TRAP: dsll32 $1, $1, 31 # encoding: [0x00,0x01,0x0f,0xfc]
|
||||
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
|
||||
# CHECK-TRAP: .Ltmp3:
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddiv $4,$5,$0
|
||||
|
|
@ -231,8 +248,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
ddiv $4,$5,1
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
|
||||
ddiv $4,$5,-1
|
||||
# CHECK-NOTRAP: dsub $4, $zero, $5 # encoding: [0x00,0x05,0x20,0x2e]
|
||||
|
|
@ -328,12 +345,10 @@
|
|||
# CHECK-NOTRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
|
||||
# CHECK-NOTRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: addiu $1, $zero, 15 # encoding: [0x24,0x01,0x00,0x0f]
|
||||
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
|
||||
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
|
||||
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
|
||||
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
|
||||
# CHECK-TRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
|
||||
# CHECK-TRAP: addiu $1, $zero, 15 # encoding: [0x24,0x01,0x00,0x0f]
|
||||
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
|
||||
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
|
||||
# CHECK-TRAP: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
|
||||
# CHECK-TRAP: ori $1, $1, 65535 # encoding: [0x34,0x21,0xff,0xff]
|
||||
# CHECK-TRAP: ddiv $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1e]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
|
|
|||
|
|
@ -1,52 +1,48 @@
|
|||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 | \
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 | \
|
||||
# RUN: FileCheck %s --check-prefix=CHECK-NOTRAP
|
||||
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r2 \
|
||||
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r2 \
|
||||
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
|
||||
|
||||
ddivu $25,$11
|
||||
# CHECK-NOTRAP: bne $11, $zero, 8 # encoding: [0x15,0x60,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $11, $zero, .Ltmp0 # encoding: [0x15,0x60,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp0-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp0
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
ddivu $24,$12
|
||||
# CHECK-NOTRAP: bne $12, $zero, 8 # encoding: [0x15,0x80,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $12, $zero, .Ltmp1 # encoding: [0x15,0x80,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp1-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp1
|
||||
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
|
||||
ddivu $25,$0
|
||||
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
ddivu $0,$9
|
||||
# CHECK-NOTRAP: bne $9, $zero, 8 # encoding: [0x15,0x20,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $9, $zero, .Ltmp2 # encoding: [0x15,0x20,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp2-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp2
|
||||
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
# CHECK-TRAP: teq $9, $zero, 7 # encoding: [0x01,0x20,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
|
||||
ddivu $0,$0
|
||||
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $zero # encoding: [0x00,0x00,0x00,0x12]
|
||||
|
||||
ddivu $4,0
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
|
|
@ -57,8 +53,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
ddivu $4,1
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
|
||||
ddivu $4,-1
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
|
|
@ -159,31 +155,23 @@
|
|||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddivu $4,$5,$6
|
||||
# CHECK-NOTRAP: bne $6, $zero, 8 # encoding: [0x14,0xc0,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $6, $zero, .Ltmp3 # encoding: [0x14,0xc0,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: .Ltmp3-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: .Ltmp3:
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddivu $4,$5,$0
|
||||
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddivu $4,$0,$0
|
||||
# CHECK-NOTRAP: bne $zero, $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: ddivu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1f]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
ddivu $0, $4, $5
|
||||
# CHECK-NOTRAP: ddivu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1f]
|
||||
|
|
@ -202,8 +190,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
ddivu $4,$5,1
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
|
||||
ddivu $4,$5,-1
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
# RUN: FileCheck %s --check-prefix=NOT-R6
|
||||
|
||||
.text
|
||||
div $25, $11
|
||||
div $25, 11
|
||||
# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
div $25, $0
|
||||
|
|
|
|||
|
|
@ -4,41 +4,55 @@
|
|||
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
|
||||
|
||||
div $25,$11
|
||||
# CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $11, $tmp0 # encoding: [0x15,0x60,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp0:
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $11, $1, 16 # encoding: [0x15,0x61,0x00,0x04]
|
||||
# CHECK-NOTRAP: bne $11, $1, $tmp1 # encoding: [0x15,0x61,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-NOTRAP: bne $25, $1, 8 # encoding: [0x17,0x21,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $25, $1, $tmp1 # encoding: [0x17,0x21,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp1:
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
# CHECK-TRAP: teq $11, $zero, 7 # encoding: [0x01,0x60,0x01,0xf4]
|
||||
# CHECK-TRAP: div $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1a]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $11, $1, 8 # encoding: [0x15,0x61,0x00,0x02]
|
||||
# CHECK-TRAP: bne $11, $1, $tmp0 # encoding: [0x15,0x61,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-TRAP: teq $25, $1, 6 # encoding: [0x03,0x21,0x01,0xb4]
|
||||
# CHECK-TRAP: $tmp0:
|
||||
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
div $24,$12
|
||||
# CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $12, $tmp2 # encoding: [0x15,0x80,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: div $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1a]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp2:
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $12, $1, 16 # encoding: [0x15,0x81,0x00,0x04]
|
||||
# CHECK-NOTRAP: bne $12, $1, $tmp3 # encoding: [0x15,0x81,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp3)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-NOTRAP: bne $24, $1, 8 # encoding: [0x17,0x01,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $24, $1, $tmp3 # encoding: [0x17,0x01,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp3)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp3:
|
||||
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
# CHECK-TRAP: teq $12, $zero, 7 # encoding: [0x01,0x80,0x01,0xf4]
|
||||
# CHECK-TRAP: div $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1a]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $12, $1, 8 # encoding: [0x15,0x81,0x00,0x02]
|
||||
# CHECK-TRAP: bne $12, $1, $tmp1 # encoding: [0x15,0x81,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-TRAP: teq $24, $1, 6 # encoding: [0x03,0x01,0x01,0xb4]
|
||||
# CHECK-TRAP: $tmp1:
|
||||
# CHECK-TRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
|
||||
div $25,$0
|
||||
|
|
@ -62,8 +76,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
div $4,1
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $4 # encoding: [0x00,0x80,0x20,0x25]
|
||||
|
||||
div $4,-1
|
||||
# CHECK-NOTRAP: neg $4, $4 # encoding: [0x00,0x04,0x20,0x22]
|
||||
|
|
@ -112,31 +126,38 @@
|
|||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
div $4,$5,$6
|
||||
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $6, $tmp4 # encoding: [0x14,0xc0,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp4)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp4:
|
||||
# CHECK-NOTRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-NOTRAP: bne $6, $1, 16 # encoding: [0x14,0xc1,0x00,0x04]
|
||||
# CHECK-NOTRAP: bne $6, $1, $tmp5 # encoding: [0x14,0xc1,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp5)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-NOTRAP: bne $5, $1, 8 # encoding: [0x14,0xa1,0x00,0x02]
|
||||
# CHECK-NOTRAP: bne $5, $1, $tmp5 # encoding: [0x14,0xa1,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp5)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: nop # encoding: [0x00,0x00,0x00,0x00]
|
||||
# CHECK-NOTRAP: break 6 # encoding: [0x00,0x06,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp5:
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: teq $6, $zero, 7 # encoding: [0x00,0xc0,0x01,0xf4]
|
||||
# CHECK-TRAP: div $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1a]
|
||||
# CHECK-TRAP: addiu $1, $zero, -1 # encoding: [0x24,0x01,0xff,0xff]
|
||||
# CHECK-TRAP: bne $6, $1, 8 # encoding: [0x14,0xc1,0x00,0x02]
|
||||
# CHECK-TRAP: bne $6, $1, $tmp2 # encoding: [0x14,0xc1,A,A]
|
||||
# CHECK-TRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-TRAP: lui $1, 32768 # encoding: [0x3c,0x01,0x80,0x00]
|
||||
# CHECK-TRAP: teq $5, $1, 6 # encoding: [0x00,0xa1,0x01,0xb4]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: $tmp2:
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
div $4,$5,$0
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
div $4,$0,$0
|
||||
# CHECK-NOTRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
|
||||
# CHECK-TRAP: div $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1a]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
div $0,$4,$5
|
||||
# CHECK-NOTRAP: div $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1a]
|
||||
|
|
@ -151,8 +172,8 @@
|
|||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
||||
div $4,$5,1
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x21]
|
||||
# CHECK-NOTRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
# CHECK-TRAP: move $4, $5 # encoding: [0x00,0xa0,0x20,0x25]
|
||||
|
||||
div $4,$5,-1
|
||||
# CHECK-NOTRAP: neg $4, $5 # encoding: [0x00,0x05,0x20,0x22]
|
||||
|
|
@ -198,4 +219,4 @@
|
|||
# CHECK-TRAP: lui $1, 1 # encoding: [0x3c,0x01,0x00,0x01]
|
||||
# CHECK-TRAP: ori $1, $1, 42405 # encoding: [0x34,0x21,0xa5,0xa5]
|
||||
# CHECK-TRAP: div $zero, $5, $1 # encoding: [0x00,0xa1,0x00,0x1a]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
# RUN: FileCheck %s --check-prefix=NOT-R6
|
||||
|
||||
.text
|
||||
divu $25, $11
|
||||
divu $25, 11
|
||||
# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
|
||||
|
||||
divu $25, $0
|
||||
|
|
|
|||
|
|
@ -4,22 +4,23 @@
|
|||
# RUN: -mattr=+use-tcc-in-div | FileCheck %s --check-prefix=CHECK-TRAP
|
||||
|
||||
divu $25,$11
|
||||
# CHECK-NOTRAP: bnez $11, 8 # encoding: [0x15,0x60,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $11, $tmp0 # encoding: [0x15,0x60,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp0)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: divu $zero, $25, $11 # encoding: [0x03,0x2b,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp0:
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
divu $24,$12
|
||||
# CHECK-NOTRAP: bnez $12, 8 # encoding: [0x15,0x80,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $12, $tmp1 # encoding: [0x15,0x80,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp1)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: divu $zero, $24, $12 # encoding: [0x03,0x0c,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp1:
|
||||
# CHECK-NOTRAP: mflo $24 # encoding: [0x00,0x00,0xc0,0x12]
|
||||
|
||||
divu $25,$0
|
||||
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
divu $0,$9
|
||||
# CHECK-NOTRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
|
||||
|
|
@ -28,22 +29,18 @@
|
|||
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
|
||||
|
||||
divu $4,$5,$6
|
||||
# CHECK-NOTRAP: bnez $6, 8 # encoding: [0x14,0xc0,0x00,0x02]
|
||||
# CHECK-NOTRAP: bnez $6, $tmp2 # encoding: [0x14,0xc0,A,A]
|
||||
# CHECK-NOTRAP: # fixup A - offset: 0, value: ($tmp2)-4, kind: fixup_Mips_PC16
|
||||
# CHECK-NOTRAP: divu $zero, $5, $6 # encoding: [0x00,0xa6,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: $tmp2:
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
divu $4,$5,$0
|
||||
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
divu $4,$0,$0
|
||||
# CHECK-NOTRAP: bnez $zero, 8 # encoding: [0x14,0x00,0x00,0x02]
|
||||
# CHECK-NOTRAP: divu $zero, $zero, $zero # encoding: [0x00,0x00,0x00,0x1b]
|
||||
# CHECK-NOTRAP: break 7 # encoding: [0x00,0x07,0x00,0x0d]
|
||||
# CHECK-NOTRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
divu $0, $4, $5
|
||||
# CHECK-NOTRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
|
||||
|
|
@ -60,8 +57,6 @@
|
|||
|
||||
divu $25,$0
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: divu $zero, $25, $zero # encoding: [0x03,0x20,0x00,0x1b]
|
||||
# CHECK-TRAP: mflo $25 # encoding: [0x00,0x00,0xc8,0x12]
|
||||
|
||||
divu $0,$9
|
||||
# CHECK-TRAP: divu $zero, $zero, $9 # encoding: [0x00,0x09,0x00,0x1b]
|
||||
|
|
@ -76,8 +71,6 @@
|
|||
|
||||
divu $4,$5,$0
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
# CHECK-TRAP: divu $zero, $5, $zero # encoding: [0x00,0xa0,0x00,0x1b]
|
||||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
divu $4,$0,$0
|
||||
# CHECK-TRAP: teq $zero, $zero, 7 # encoding: [0x00,0x00,0x01,0xf4]
|
||||
|
|
@ -85,4 +78,4 @@
|
|||
# CHECK-TRAP: mflo $4 # encoding: [0x00,0x00,0x20,0x12]
|
||||
|
||||
divu $0, $4, $5
|
||||
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
|
||||
# CHECK-TRAP: divu $zero, $4, $5 # encoding: [0x00,0x85,0x00,0x1b]
|
||||
|
|
|
|||
Loading…
Reference in New Issue