forked from OSchip/llvm-project
R600/SI: Remove some unnecessary patterns from VINTRP multiclass
DisableEncoding and Constraints can be set using let statements around the multiclass defs. llvm-svn: 238148
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@ -1771,16 +1771,12 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
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SIMCInstr<opName, SISubtarget.VI>;
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multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
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list<dag> pattern = [],
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string disableEncoding = "", string constraints = ""> {
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let DisableEncoding = disableEncoding,
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Constraints = constraints in {
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def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
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list<dag> pattern = []> {
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def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
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def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
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def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
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def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
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}
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def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
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}
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//===----------------------------------------------------------------------===//
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@ -1461,15 +1461,17 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
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} // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst"
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let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in {
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defm V_INTERP_P2_F32 : VINTRP_m <
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0x00000001,
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(outs VGPR_32:$dst),
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(ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr),
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"v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]",
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[(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan),
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(i32 imm:$attr)))],
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"$src0",
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"$src0 = $dst">;
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(i32 imm:$attr)))]>;
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} // End DisableEncoding = "$src0", Constraints = "$src0 = $dst"
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defm V_INTERP_MOV_F32 : VINTRP_m <
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0x00000002,
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