MIR Serialization: Change MIR syntax - use custom syntax for MBBs.

This commit modifies the way the machine basic blocks are serialized - now the
machine basic blocks are serialized using a custom syntax instead of relying on
YAML primitives. Instead of using YAML mappings to represent the individual
machine basic blocks in a machine function's body, the new syntax uses a single
YAML block scalar which contains all of the machine basic blocks and
instructions for that function.

This is an example of a function's body that uses the old syntax:

    body:
      - id: 0
        name: entry
        instructions:
          - '%eax = MOV32r0 implicit-def %eflags'
          - 'RETQ %eax'
    ...

The same body is now written like this:

    body: |
      bb.0.entry:
        %eax = MOV32r0 implicit-def %eflags
        RETQ %eax
    ...

This syntax change is motivated by the fact that the bundled machine
instructions didn't map that well to the old syntax which was using a single
YAML sequence to store all of the machine instructions in a block. The bundled
machine instructions internally use flags like BundledPred and BundledSucc to
determine the bundles, and serializing them as MI flags using the old syntax
would have had a negative impact on the readability and the ease of editing
for MIR files. The new syntax allows me to serialize the bundled machine
instructions using a block construct without relying on the internal flags,
for example:

   BUNDLE implicit-def dead %itstate, implicit-def %s1 ... {
      t2IT 1, 24, implicit-def %itstate
      %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate
   }

This commit also converts the MIR testcases to the new syntax. I developed
a script that can convert from the old syntax to the new one. I will post the
script on the llvm-commits mailing list in the thread for this commit.

llvm-svn: 244982

llvm/include/llvm/CodeGen/MIRYamlMapping.h

@@ -73,6 +73,20 @@ template <> struct ScalarTraits<FlowStringValue> {
   static bool mustQuote(StringRef Scalar) { return needsQuotes(Scalar); }
 };
 
+struct BlockStringValue {
+  StringValue Value;
+};
+
+template <> struct BlockScalarTraits<BlockStringValue> {
+  static void output(const BlockStringValue &S, void *Ctx, raw_ostream &OS) {
+    return ScalarTraits<StringValue>::output(S.Value, Ctx, OS);
+  }
+
+  static StringRef input(StringRef Scalar, void *Ctx, BlockStringValue &S) {
+    return ScalarTraits<StringValue>::input(Scalar, Ctx, S.Value);
+  }
+};
+
 /// A wrapper around unsigned which contains a source range that's being set
 /// during parsing.
 struct UnsignedValue {
@@ -164,36 +178,6 @@ template <> struct MappingTraits<MachineFunctionLiveIn> {
   static const bool flow = true;
 };
 
-struct MachineBasicBlock {
-  unsigned ID;
-  StringValue Name;
-  StringValue IRBlock;
-  unsigned Alignment = 0;
-  bool IsLandingPad = false;
-  bool AddressTaken = false;
-  std::vector<FlowStringValue> Successors;
-  std::vector<UnsignedValue> SuccessorWeights;
-  std::vector<FlowStringValue> LiveIns;
-  std::vector<StringValue> Instructions;
-};
-
-template <> struct MappingTraits<MachineBasicBlock> {
-  static void mapping(IO &YamlIO, MachineBasicBlock &MBB) {
-    YamlIO.mapRequired("id", MBB.ID);
-    YamlIO.mapOptional("name", MBB.Name,
-                       StringValue()); // Don't print out an empty name.
-    YamlIO.mapOptional("ir-block", MBB.IRBlock,
-                       StringValue()); // Don't print out an empty BB reference.
-    YamlIO.mapOptional("alignment", MBB.Alignment);
-    YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
-    YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
-    YamlIO.mapOptional("successors", MBB.Successors);
-    YamlIO.mapOptional("weights", MBB.SuccessorWeights);
-    YamlIO.mapOptional("liveins", MBB.LiveIns);
-    YamlIO.mapOptional("instructions", MBB.Instructions);
-  }
-};
-
 /// Serializable representation of stack object from the MachineFrameInfo class.
 ///
 /// The flags 'isImmutable' and 'isAliased' aren't serialized, as they are
@@ -320,7 +304,6 @@ template <> struct MappingTraits<MachineJumpTable::Entry> {
 
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineFunctionLiveIn)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::VirtualRegisterDefinition)
-LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineStackObject)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::FixedMachineStackObject)
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineConstantPoolValue)
@@ -404,8 +387,7 @@ struct MachineFunction {
   std::vector<MachineStackObject> StackObjects;
   std::vector<MachineConstantPoolValue> Constants; /// Constant pool.
   MachineJumpTable JumpTableInfo;
-
-  std::vector<MachineBasicBlock> BasicBlocks;
+  BlockStringValue Body;
 };
 
 template <> struct MappingTraits<MachineFunction> {
@@ -426,7 +408,7 @@ template <> struct MappingTraits<MachineFunction> {
     YamlIO.mapOptional("constants", MF.Constants);
     if (!YamlIO.outputting() || !MF.JumpTableInfo.Entries.empty())
       YamlIO.mapOptional("jumpTable", MF.JumpTableInfo);
-    YamlIO.mapOptional("body", MF.BasicBlocks);
+    YamlIO.mapOptional("body", MF.Body);
   }
 };
 

llvm/include/llvm/CodeGen/MachineBasicBlock.h

@@ -25,7 +25,7 @@ class Pass;
 class BasicBlock;
 class MachineFunction;
 class MCSymbol;
-class MIRPrinter;
+class MIPrinter;
 class SlotIndexes;
 class StringRef;
 class raw_ostream;
@@ -660,7 +660,7 @@ private:
   const_weight_iterator getWeightIterator(const_succ_iterator I) const;
 
   friend class MachineBranchProbabilityInfo;
-  friend class MIRPrinter;
+  friend class MIPrinter;
 
   /// Return weight of the edge from this block to MBB. This method should NOT
   /// be called directly, but by using getEdgeWeight method from

llvm/lib/CodeGen/MIRParser/MILexer.cpp

@@ -79,7 +79,18 @@ MIToken &MIToken::setIntegerValue(APSInt IntVal) {
 
 /// Skip the leading whitespace characters and return the updated cursor.
 static Cursor skipWhitespace(Cursor C) {
-  while (isspace(C.peek()))
+  while (isblank(C.peek()))
+    C.advance();
+  return C;
+}
+
+static bool isNewlineChar(char C) { return C == '\n' || C == '\r'; }
+
+/// Skip a line comment and return the updated cursor.
+static Cursor skipComment(Cursor C) {
+  if (C.peek() != ';')
+    return C;
+  while (!isNewlineChar(C.peek()) && !C.isEOF())
     C.advance();
   return C;
 }
@@ -127,7 +138,7 @@ static Cursor lexStringConstant(
     function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
   assert(C.peek() == '"');
   for (C.advance(); C.peek() != '"'; C.advance()) {
-    if (C.isEOF()) {
+    if (C.isEOF() || isNewlineChar(C.peek())) {
       ErrorCallback(
           C.location(),
           "end of machine instruction reached before the closing '\"'");
@@ -206,6 +217,10 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
       .Case("jump-table", MIToken::kw_jump_table)
       .Case("constant-pool", MIToken::kw_constant_pool)
       .Case("liveout", MIToken::kw_liveout)
+      .Case("address-taken", MIToken::kw_address_taken)
+      .Case("landing-pad", MIToken::kw_landing_pad)
+      .Case("liveins", MIToken::kw_liveins)
+      .Case("successors", MIToken::kw_successors)
       .Default(MIToken::Identifier);
 }
 
@@ -224,10 +239,12 @@ static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
 static Cursor maybeLexMachineBasicBlock(
     Cursor C, MIToken &Token,
     function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
-  if (!C.remaining().startswith("%bb."))
+  bool IsReference = C.remaining().startswith("%bb.");
+  if (!IsReference && !C.remaining().startswith("bb."))
     return None;
   auto Range = C;
-  C.advance(4); // Skip '%bb.'
+  unsigned PrefixLength = IsReference ? 4 : 3;
+  C.advance(PrefixLength); // Skip '%bb.' or 'bb.'
   if (!isdigit(C.peek())) {
     Token.reset(MIToken::Error, C.remaining());
     ErrorCallback(C.location(), "expected a number after '%bb.'");
@@ -237,14 +254,16 @@ static Cursor maybeLexMachineBasicBlock(
   while (isdigit(C.peek()))
     C.advance();
   StringRef Number = NumberRange.upto(C);
-  unsigned StringOffset = 4 + Number.size(); // Drop '%bb.<id>'
+  unsigned StringOffset = PrefixLength + Number.size(); // Drop '%bb.<id>'
   if (C.peek() == '.') {
     C.advance(); // Skip '.'
     ++StringOffset;
     while (isIdentifierChar(C.peek()))
       C.advance();
   }
-  Token.reset(MIToken::MachineBasicBlock, Range.upto(C))
+  Token.reset(IsReference ? MIToken::MachineBasicBlock
+                          : MIToken::MachineBasicBlockLabel,
+              Range.upto(C))
       .setIntegerValue(APSInt(Number))
       .setStringValue(Range.upto(C).drop_front(StringOffset));
   return C;
@@ -460,10 +479,19 @@ static Cursor maybeLexSymbol(Cursor C, MIToken &Token) {
   return C;
 }
 
+static Cursor maybeLexNewline(Cursor C, MIToken &Token) {
+  if (!isNewlineChar(C.peek()))
+    return None;
+  auto Range = C;
+  C.advance();
+  Token.reset(MIToken::Newline, Range.upto(C));
+  return C;
+}
+
 StringRef llvm::lexMIToken(
     StringRef Source, MIToken &Token,
     function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
-  auto C = skipWhitespace(Cursor(Source));
+  auto C = skipComment(skipWhitespace(Cursor(Source)));
   if (C.isEOF()) {
     Token.reset(MIToken::Eof, C.remaining());
     return C.remaining();
@@ -471,10 +499,10 @@ StringRef llvm::lexMIToken(
 
   if (Cursor R = maybeLexIntegerType(C, Token))
     return R.remaining();
-  if (Cursor R = maybeLexIdentifier(C, Token))
-    return R.remaining();
   if (Cursor R = maybeLexMachineBasicBlock(C, Token, ErrorCallback))
     return R.remaining();
+  if (Cursor R = maybeLexIdentifier(C, Token))
+    return R.remaining();
   if (Cursor R = maybeLexJumpTableIndex(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexStackObject(C, Token))
@@ -499,6 +527,8 @@ StringRef llvm::lexMIToken(
     return R.remaining();
   if (Cursor R = maybeLexSymbol(C, Token))
     return R.remaining();
+  if (Cursor R = maybeLexNewline(C, Token))
+    return R.remaining();
 
   Token.reset(MIToken::Error, C.remaining());
   ErrorCallback(C.location(),

llvm/lib/CodeGen/MIRParser/MILexer.h

@@ -30,6 +30,7 @@ struct MIToken {
     // Markers
     Eof,
     Error,
+    Newline,
 
     // Tokens with no info.
     comma,
@@ -75,11 +76,16 @@ struct MIToken {
     kw_jump_table,
     kw_constant_pool,
     kw_liveout,
+    kw_address_taken,
+    kw_landing_pad,
+    kw_liveins,
+    kw_successors,
 
     // Identifier tokens
     Identifier,
     IntegerType,
     NamedRegister,
+    MachineBasicBlockLabel,
     MachineBasicBlock,
     StackObject,
     FixedStackObject,
@@ -118,6 +124,10 @@ public:
 
   bool isError() const { return Kind == Error; }
 
+  bool isNewlineOrEOF() const { return Kind == Newline || Kind == Eof; }
+
+  bool isErrorOrEOF() const { return Kind == Error || Kind == Eof; }
+
   bool isRegister() const {
     return Kind == NamedRegister || Kind == underscore ||
            Kind == VirtualRegister;
@@ -149,10 +159,10 @@ public:
 
   bool hasIntegerValue() const {
     return Kind == IntegerLiteral || Kind == MachineBasicBlock ||
-           Kind == StackObject || Kind == FixedStackObject ||
-           Kind == GlobalValue || Kind == VirtualRegister ||
-           Kind == ConstantPoolItem || Kind == JumpTableIndex ||
-           Kind == IRBlock;
+           Kind == MachineBasicBlockLabel || Kind == StackObject ||
+           Kind == FixedStackObject || Kind == GlobalValue ||
+           Kind == VirtualRegister || Kind == ConstantPoolItem ||
+           Kind == JumpTableIndex || Kind == IRBlock;
   }
 };
 

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -90,11 +90,19 @@ public:
   /// This function always return true.
   bool error(StringRef::iterator Loc, const Twine &Msg);
 
+  bool
+  parseBasicBlockDefinitions(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
+  bool parseBasicBlocks();
   bool parse(MachineInstr *&MI);
   bool parseStandaloneMBB(MachineBasicBlock *&MBB);
   bool parseStandaloneNamedRegister(unsigned &Reg);
   bool parseStandaloneVirtualRegister(unsigned &Reg);
-  bool parseStandaloneIRBlockReference(const BasicBlock *&BB);
+
+  bool
+  parseBasicBlockDefinition(DenseMap<unsigned, MachineBasicBlock *> &MBBSlots);
+  bool parseBasicBlock(MachineBasicBlock &MBB);
+  bool parseBasicBlockLiveins(MachineBasicBlock &MBB);
+  bool parseBasicBlockSuccessors(MachineBasicBlock &MBB);
 
   bool parseRegister(unsigned &Reg);
   bool parseRegisterFlag(unsigned &Flags);
@@ -149,6 +157,10 @@ private:
   /// Otherwise report an error and return true.
   bool expectAndConsume(MIToken::TokenKind TokenKind);
 
+  /// If the current token is of the given kind, consume it and return true.
+  /// Otherwise return false.
+  bool consumeIfPresent(MIToken::TokenKind TokenKind);
+
   void initNames2InstrOpCodes();
 
   /// Try to convert an instruction name to an opcode. Return true if the
@@ -217,10 +229,17 @@ bool MIParser::error(const Twine &Msg) { return error(Token.location(), Msg); }
 
 bool MIParser::error(StringRef::iterator Loc, const Twine &Msg) {
   assert(Loc >= Source.data() && Loc <= (Source.data() + Source.size()));
-  Error = SMDiagnostic(
-      SM, SMLoc(),
-      SM.getMemoryBuffer(SM.getMainFileID())->getBufferIdentifier(), 1,
-      Loc - Source.data(), SourceMgr::DK_Error, Msg.str(), Source, None, None);
+  const MemoryBuffer &Buffer = *SM.getMemoryBuffer(SM.getMainFileID());
+  if (Loc >= Buffer.getBufferStart() && Loc <= Buffer.getBufferEnd()) {
+    // Create an ordinary diagnostic when the source manager's buffer is the
+    // source string.
+    Error = SM.GetMessage(SMLoc::getFromPointer(Loc), SourceMgr::DK_Error, Msg);
+    return true;
+  }
+  // Create a diagnostic for a YAML string literal.
+  Error = SMDiagnostic(SM, SMLoc(), Buffer.getBufferIdentifier(), 1,
+                       Loc - Source.data(), SourceMgr::DK_Error, Msg.str(),
+                       Source, None, None);
   return true;
 }
 
@@ -230,6 +249,8 @@ static const char *toString(MIToken::TokenKind TokenKind) {
     return "','";
   case MIToken::equal:
     return "'='";
+  case MIToken::colon:
+    return "':'";
   case MIToken::lparen:
     return "'('";
   case MIToken::rparen:
@@ -246,9 +267,236 @@ bool MIParser::expectAndConsume(MIToken::TokenKind TokenKind) {
   return false;
 }
 
-bool MIParser::parse(MachineInstr *&MI) {
+bool MIParser::consumeIfPresent(MIToken::TokenKind TokenKind) {
+  if (Token.isNot(TokenKind))
+    return false;
   lex();
+  return true;
+}
 
+bool MIParser::parseBasicBlockDefinition(
+    DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {
+  assert(Token.is(MIToken::MachineBasicBlockLabel));
+  unsigned ID = 0;
+  if (getUnsigned(ID))
+    return true;
+  auto Loc = Token.location();
+  auto Name = Token.stringValue();
+  lex();
+  bool HasAddressTaken = false;
+  bool IsLandingPad = false;
+  unsigned Alignment = 0;
+  BasicBlock *BB = nullptr;
+  if (consumeIfPresent(MIToken::lparen)) {
+    do {
+      // TODO: Report an error when multiple same attributes are specified.
+      switch (Token.kind()) {
+      case MIToken::kw_address_taken:
+        HasAddressTaken = true;
+        lex();
+        break;
+      case MIToken::kw_landing_pad:
+        IsLandingPad = true;
+        lex();
+        break;
+      case MIToken::kw_align:
+        if (parseAlignment(Alignment))
+          return true;
+        break;
+      case MIToken::IRBlock:
+        // TODO: Report an error when both name and ir block are specified.
+        if (parseIRBlock(BB, *MF.getFunction()))
+          return true;
+        lex();
+        break;
+      default:
+        break;
+      }
+    } while (consumeIfPresent(MIToken::comma));
+    if (expectAndConsume(MIToken::rparen))
+      return true;
+  }
+  if (expectAndConsume(MIToken::colon))
+    return true;
+
+  if (!Name.empty()) {
+    BB = dyn_cast_or_null<BasicBlock>(
+        MF.getFunction()->getValueSymbolTable().lookup(Name));
+    if (!BB)
+      return error(Loc, Twine("basic block '") + Name +
+                            "' is not defined in the function '" +
+                            MF.getName() + "'");
+  }
+  auto *MBB = MF.CreateMachineBasicBlock(BB);
+  MF.insert(MF.end(), MBB);
+  bool WasInserted = MBBSlots.insert(std::make_pair(ID, MBB)).second;
+  if (!WasInserted)
+    return error(Loc, Twine("redefinition of machine basic block with id #") +
+                          Twine(ID));
+  if (Alignment)
+    MBB->setAlignment(Alignment);
+  if (HasAddressTaken)
+    MBB->setHasAddressTaken();
+  MBB->setIsLandingPad(IsLandingPad);
+  return false;
+}
+
+bool MIParser::parseBasicBlockDefinitions(
+    DenseMap<unsigned, MachineBasicBlock *> &MBBSlots) {
+  lex();
+  // Skip until the first machine basic block.
+  while (Token.is(MIToken::Newline))
+    lex();
+  if (Token.isErrorOrEOF())
+    return Token.isError();
+  if (Token.isNot(MIToken::MachineBasicBlockLabel))
+    return error("expected a basic block definition before instructions");
+  do {
+    if (parseBasicBlockDefinition(MBBSlots))
+      return true;
+    bool IsAfterNewline = false;
+    // Skip until the next machine basic block.
+    while (true) {
+      if ((Token.is(MIToken::MachineBasicBlockLabel) && IsAfterNewline) ||
+          Token.isErrorOrEOF())
+        break;
+      else if (Token.is(MIToken::MachineBasicBlockLabel))
+        return error("basic block definition should be located at the start of "
+                     "the line");
+      if (Token.is(MIToken::Newline))
+        IsAfterNewline = true;
+      else
+        IsAfterNewline = false;
+      lex();
+    }
+  } while (!Token.isErrorOrEOF());
+  return Token.isError();
+}
+
+bool MIParser::parseBasicBlockLiveins(MachineBasicBlock &MBB) {
+  assert(Token.is(MIToken::kw_liveins));
+  lex();
+  if (expectAndConsume(MIToken::colon))
+    return true;
+  if (Token.isNewlineOrEOF()) // Allow an empty list of liveins.
+    return false;
+  do {
+    if (Token.isNot(MIToken::NamedRegister))
+      return error("expected a named register");
+    unsigned Reg = 0;
+    if (parseRegister(Reg))
+      return true;
+    MBB.addLiveIn(Reg);
+    lex();
+  } while (consumeIfPresent(MIToken::comma));
+  return false;
+}
+
+bool MIParser::parseBasicBlockSuccessors(MachineBasicBlock &MBB) {
+  assert(Token.is(MIToken::kw_successors));
+  lex();
+  if (expectAndConsume(MIToken::colon))
+    return true;
+  if (Token.isNewlineOrEOF()) // Allow an empty list of successors.
+    return false;
+  do {
+    if (Token.isNot(MIToken::MachineBasicBlock))
+      return error("expected a machine basic block reference");
+    MachineBasicBlock *SuccMBB = nullptr;
+    if (parseMBBReference(SuccMBB))
+      return true;
+    lex();
+    unsigned Weight = 0;
+    if (consumeIfPresent(MIToken::lparen)) {
+      if (Token.isNot(MIToken::IntegerLiteral))
+        return error("expected an integer literal after '('");
+      if (getUnsigned(Weight))
+        return true;
+      lex();
+      if (expectAndConsume(MIToken::rparen))
+        return true;
+    }
+    MBB.addSuccessor(SuccMBB, Weight);
+  } while (consumeIfPresent(MIToken::comma));
+  return false;
+}
+
+bool MIParser::parseBasicBlock(MachineBasicBlock &MBB) {
+  // Skip the definition.
+  assert(Token.is(MIToken::MachineBasicBlockLabel));
+  lex();
+  if (consumeIfPresent(MIToken::lparen)) {
+    while (Token.isNot(MIToken::rparen) && !Token.isErrorOrEOF())
+      lex();
+    consumeIfPresent(MIToken::rparen);
+  }
+  consumeIfPresent(MIToken::colon);
+
+  // Parse the liveins and successors.
+  // N.B: Multiple lists of successors and liveins are allowed and they're
+  // merged into one.
+  // Example:
+  //   liveins: %edi
+  //   liveins: %esi
+  //
+  // is equivalent to
+  //   liveins: %edi, %esi
+  while (true) {
+    if (Token.is(MIToken::kw_successors)) {
+      if (parseBasicBlockSuccessors(MBB))
+        return true;
+    } else if (Token.is(MIToken::kw_liveins)) {
+      if (parseBasicBlockLiveins(MBB))
+        return true;
+    } else if (consumeIfPresent(MIToken::Newline)) {
+      continue;
+    } else
+      break;
+    if (!Token.isNewlineOrEOF())
+      return error("expected line break at the end of a list");
+    lex();
+  }
+
+  // Parse the instructions.
+  while (true) {
+    if (Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof))
+      return false;
+    else if (consumeIfPresent(MIToken::Newline))
+      continue;
+    MachineInstr *MI = nullptr;
+    if (parse(MI))
+      return true;
+    MBB.insert(MBB.end(), MI);
+    assert(Token.isNewlineOrEOF() && "MI is not fully parsed");
+    lex();
+  }
+  return false;
+}
+
+bool MIParser::parseBasicBlocks() {
+  lex();
+  // Skip until the first machine basic block.
+  while (Token.is(MIToken::Newline))
+    lex();
+  if (Token.isErrorOrEOF())
+    return Token.isError();
+  // The first parsing pass should have verified that this token is a MBB label
+  // in the 'parseBasicBlockDefinitions' method.
+  assert(Token.is(MIToken::MachineBasicBlockLabel));
+  do {
+    MachineBasicBlock *MBB = nullptr;
+    if (parseMBBReference(MBB))
+      return true;
+    if (parseBasicBlock(*MBB))
+      return true;
+    // The method 'parseBasicBlock' should parse the whole block until the next
+    // block or the end of file.
+    assert(Token.is(MIToken::MachineBasicBlockLabel) || Token.is(MIToken::Eof));
+  } while (Token.isNot(MIToken::Eof));
+  return false;
+}
+
+bool MIParser::parse(MachineInstr *&MI) {
   // Parse any register operands before '='
   MachineOperand MO = MachineOperand::CreateImm(0);
   SmallVector<MachineOperandWithLocation, 8> Operands;
@@ -271,13 +519,13 @@ bool MIParser::parse(MachineInstr *&MI) {
   // TODO: Parse the bundle instruction flags.
 
   // Parse the remaining machine operands.
-  while (Token.isNot(MIToken::Eof) && Token.isNot(MIToken::kw_debug_location) &&
+  while (!Token.isNewlineOrEOF() && Token.isNot(MIToken::kw_debug_location) &&
          Token.isNot(MIToken::coloncolon)) {
     auto Loc = Token.location();
     if (parseMachineOperandAndTargetFlags(MO))
       return true;
     Operands.push_back(MachineOperandWithLocation(MO, Loc, Token.location()));
-    if (Token.is(MIToken::Eof) || Token.is(MIToken::coloncolon))
+    if (Token.isNewlineOrEOF() || Token.is(MIToken::coloncolon))
       break;
     if (Token.isNot(MIToken::comma))
       return error("expected ',' before the next machine operand");
@@ -299,12 +547,12 @@ bool MIParser::parse(MachineInstr *&MI) {
   SmallVector<MachineMemOperand *, 2> MemOperands;
   if (Token.is(MIToken::coloncolon)) {
     lex();
-    while (Token.isNot(MIToken::Eof)) {
+    while (!Token.isNewlineOrEOF()) {
       MachineMemOperand *MemOp = nullptr;
       if (parseMachineMemoryOperand(MemOp))
         return true;
       MemOperands.push_back(MemOp);
-      if (Token.is(MIToken::Eof))
+      if (Token.isNewlineOrEOF())
         break;
       if (Token.isNot(MIToken::comma))
         return error("expected ',' before the next machine memory operand");
@@ -370,23 +618,6 @@ bool MIParser::parseStandaloneVirtualRegister(unsigned &Reg) {
   return false;
 }
 
-bool MIParser::parseStandaloneIRBlockReference(const BasicBlock *&BB) {
-  lex();
-  if (Token.isNot(MIToken::IRBlock))
-    return error("expected an IR block reference");
-  unsigned SlotNumber = 0;
-  if (getUnsigned(SlotNumber))
-    return true;
-  BB = getIRBlock(SlotNumber);
-  if (!BB)
-    return error(Twine("use of undefined IR block '%ir-block.") +
-                 Twine(SlotNumber) + "'");
-  lex();
-  if (Token.isNot(MIToken::Eof))
-    return error("expected end of string after the IR block reference");
-  return false;
-}
-
 static const char *printImplicitRegisterFlag(const MachineOperand &MO) {
   assert(MO.isImplicit());
   return MO.isDef() ? "implicit-def" : "implicit";
@@ -621,7 +852,8 @@ bool MIParser::getUnsigned(unsigned &Result) {
 }
 
 bool MIParser::parseMBBReference(MachineBasicBlock *&MBB) {
-  assert(Token.is(MIToken::MachineBasicBlock));
+  assert(Token.is(MIToken::MachineBasicBlock) ||
+         Token.is(MIToken::MachineBasicBlockLabel));
   unsigned Number;
   if (getUnsigned(Number))
     return true;
@@ -1406,11 +1638,27 @@ bool MIParser::getDirectTargetFlag(StringRef Name, unsigned &Flag) {
   return false;
 }
 
-bool llvm::parseMachineInstr(MachineInstr *&MI, SourceMgr &SM,
-                             MachineFunction &MF, StringRef Src,
+bool llvm::parseMachineBasicBlockDefinitions(MachineFunction &MF, StringRef Src,
+                                             PerFunctionMIParsingState &PFS,
+                                             const SlotMapping &IRSlots,
+                                             SMDiagnostic &Error) {
+  SourceMgr SM;
+  SM.AddNewSourceBuffer(
+      MemoryBuffer::getMemBuffer(Src, "", /*RequiresNullTerminator=*/false),
+      SMLoc());
+  return MIParser(SM, MF, Error, Src, PFS, IRSlots)
+      .parseBasicBlockDefinitions(PFS.MBBSlots);
+}
+
+bool llvm::parseMachineInstructions(MachineFunction &MF, StringRef Src,
                                     const PerFunctionMIParsingState &PFS,
-                             const SlotMapping &IRSlots, SMDiagnostic &Error) {
-  return MIParser(SM, MF, Error, Src, PFS, IRSlots).parse(MI);
+                                    const SlotMapping &IRSlots,
+                                    SMDiagnostic &Error) {
+  SourceMgr SM;
+  SM.AddNewSourceBuffer(
+      MemoryBuffer::getMemBuffer(Src, "", /*RequiresNullTerminator=*/false),
+      SMLoc());
+  return MIParser(SM, MF, Error, Src, PFS, IRSlots).parseBasicBlocks();
 }
 
 bool llvm::parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
@@ -1437,12 +1685,3 @@ bool llvm::parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
   return MIParser(SM, MF, Error, Src, PFS, IRSlots)
       .parseStandaloneVirtualRegister(Reg);
 }
-
-bool llvm::parseIRBlockReference(const BasicBlock *&BB, SourceMgr &SM,
-                                 MachineFunction &MF, StringRef Src,
-                                 const PerFunctionMIParsingState &PFS,
-                                 const SlotMapping &IRSlots,
-                                 SMDiagnostic &Error) {
-  return MIParser(SM, MF, Error, Src, PFS, IRSlots)
-      .parseStandaloneIRBlockReference(BB);
-}

llvm/lib/CodeGen/MIRParser/MIParser.h

@@ -36,8 +36,35 @@ struct PerFunctionMIParsingState {
   DenseMap<unsigned, unsigned> JumpTableSlots;
 };
 
-bool parseMachineInstr(MachineInstr *&MI, SourceMgr &SM, MachineFunction &MF,
-                       StringRef Src, const PerFunctionMIParsingState &PFS,
+/// Parse the machine basic block definitions, and skip the machine
+/// instructions.
+///
+/// This function runs the first parsing pass on the machine function's body.
+/// It parses only the machine basic block definitions and creates the machine
+/// basic blocks in the given machine function.
+///
+/// The machine instructions aren't parsed during the first pass because all
+/// the machine basic blocks aren't defined yet - this makes it impossible to
+/// resolve the machine basic block references.
+///
+/// Return true if an error occurred.
+bool parseMachineBasicBlockDefinitions(MachineFunction &MF, StringRef Src,
+                                       PerFunctionMIParsingState &PFS,
+                                       const SlotMapping &IRSlots,
+                                       SMDiagnostic &Error);
+
+/// Parse the machine instructions.
+///
+/// This function runs the second parsing pass on the machine function's body.
+/// It skips the machine basic block definitions and parses only the machine
+/// instructions and basic block attributes like liveins and successors.
+///
+/// The second parsing pass assumes that the first parsing pass already ran
+/// on the given source string.
+///
+/// Return true if an error occurred.
+bool parseMachineInstructions(MachineFunction &MF, StringRef Src,
+                              const PerFunctionMIParsingState &PFS,
                               const SlotMapping &IRSlots, SMDiagnostic &Error);
 
 bool parseMBBReference(MachineBasicBlock *&MBB, SourceMgr &SM,
@@ -57,11 +84,6 @@ bool parseVirtualRegisterReference(unsigned &Reg, SourceMgr &SM,
                                    const SlotMapping &IRSlots,
                                    SMDiagnostic &Error);
 
-bool parseIRBlockReference(const BasicBlock *&BB, SourceMgr &SM,
-                           MachineFunction &MF, StringRef Src,
-                           const PerFunctionMIParsingState &PFS,
-                           const SlotMapping &IRSlots, SMDiagnostic &Error);
-
 } // end namespace llvm
 
 #endif

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

@@ -96,13 +96,6 @@ public:
   /// Return true if error occurred.
   bool initializeMachineFunction(MachineFunction &MF);
 
-  /// Initialize the machine basic block using it's YAML representation.
-  ///
-  /// Return true if an error occurred.
-  bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
-                                   const yaml::MachineBasicBlock &YamlMBB,
-                                   const PerFunctionMIParsingState &PFS);
-
   bool initializeRegisterInfo(MachineFunction &MF,
                               const yaml::MachineFunction &YamlMF,
                               PerFunctionMIParsingState &PFS);
@@ -294,36 +287,15 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
       return true;
   }
 
-  const auto &F = *MF.getFunction();
-  for (const auto &YamlMBB : YamlMF.BasicBlocks) {
-    const BasicBlock *BB = nullptr;
-    const yaml::StringValue &Name = YamlMBB.Name;
-    const yaml::StringValue &IRBlock = YamlMBB.IRBlock;
-    if (!Name.Value.empty()) {
-      BB = dyn_cast_or_null<BasicBlock>(
-          F.getValueSymbolTable().lookup(Name.Value));
-      if (!BB)
-        return error(Name.SourceRange.Start,
-                     Twine("basic block '") + Name.Value +
-                         "' is not defined in the function '" + MF.getName() +
-                         "'");
-    }
-    if (!IRBlock.Value.empty()) {
-      // TODO: Report an error when both name and ir block are specified.
   SMDiagnostic Error;
-      if (parseIRBlockReference(BB, SM, MF, IRBlock.Value, PFS, IRSlots, Error))
-        return error(Error, IRBlock.SourceRange);
-    }
-    auto *MBB = MF.CreateMachineBasicBlock(BB);
-    MF.insert(MF.end(), MBB);
-    bool WasInserted =
-        PFS.MBBSlots.insert(std::make_pair(YamlMBB.ID, MBB)).second;
-    if (!WasInserted)
-      return error(Twine("redefinition of machine basic block with id #") +
-                   Twine(YamlMBB.ID));
+  if (parseMachineBasicBlockDefinitions(MF, YamlMF.Body.Value.Value, PFS,
+                                        IRSlots, Error)) {
+    reportDiagnostic(
+        diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
+    return true;
   }
 
-  if (YamlMF.BasicBlocks.empty())
+  if (MF.empty())
     return error(Twine("machine function '") + Twine(MF.getName()) +
                  "' requires at least one machine basic block in its body");
   // Initialize the frame information after creating all the MBBs so that the
@@ -335,12 +307,12 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   if (!YamlMF.JumpTableInfo.Entries.empty() &&
       initializeJumpTableInfo(MF, YamlMF.JumpTableInfo, PFS))
     return true;
-  // Initialize the machine basic blocks after creating them all so that the
-  // machine instructions parser can resolve the MBB references.
-  unsigned I = 0;
-  for (const auto &YamlMBB : YamlMF.BasicBlocks) {
-    if (initializeMachineBasicBlock(MF, *MF.getBlockNumbered(I++), YamlMBB,
-                                    PFS))
+  // Parse the machine instructions after creating all of the MBBs so that the
+  // parser can resolve the MBB references.
+  if (parseMachineInstructions(MF, YamlMF.Body.Value.Value, PFS, IRSlots,
+                               Error)) {
+    reportDiagnostic(
+        diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
     return true;
   }
   inferRegisterInfo(MF, YamlMF);
@@ -351,53 +323,6 @@ bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   return false;
 }
 
-bool MIRParserImpl::initializeMachineBasicBlock(
-    MachineFunction &MF, MachineBasicBlock &MBB,
-    const yaml::MachineBasicBlock &YamlMBB,
-    const PerFunctionMIParsingState &PFS) {
-  MBB.setAlignment(YamlMBB.Alignment);
-  if (YamlMBB.AddressTaken)
-    MBB.setHasAddressTaken();
-  MBB.setIsLandingPad(YamlMBB.IsLandingPad);
-  SMDiagnostic Error;
-  // Parse the successors.
-  const auto &Weights = YamlMBB.SuccessorWeights;
-  bool HasWeights = !Weights.empty();
-  if (HasWeights && Weights.size() != YamlMBB.Successors.size()) {
-    bool IsFew = Weights.size() < YamlMBB.Successors.size();
-    return error(IsFew ? Weights.back().SourceRange.End
-                       : Weights[YamlMBB.Successors.size()].SourceRange.Start,
-                 Twine("too ") + (IsFew ? "few" : "many") +
-                     " successor weights, expected " +
-                     Twine(YamlMBB.Successors.size()) + ", have " +
-                     Twine(Weights.size()));
-  }
-  size_t SuccessorIndex = 0;
-  for (const auto &MBBSource : YamlMBB.Successors) {
-    MachineBasicBlock *SuccMBB = nullptr;
-    if (parseMBBReference(SuccMBB, MBBSource, MF, PFS))
-      return true;
-    // TODO: Report an error when adding the same successor more than once.
-    MBB.addSuccessor(SuccMBB, HasWeights ? Weights[SuccessorIndex++].Value : 0);
-  }
-  // Parse the liveins.
-  for (const auto &LiveInSource : YamlMBB.LiveIns) {
-    unsigned Reg = 0;
-    if (parseNamedRegisterReference(Reg, SM, MF, LiveInSource.Value, PFS,
-                                    IRSlots, Error))
-      return error(Error, LiveInSource.SourceRange);
-    MBB.addLiveIn(Reg);
-  }
-  // Parse the instructions.
-  for (const auto &MISource : YamlMBB.Instructions) {
-    MachineInstr *MI = nullptr;
-    if (parseMachineInstr(MI, SM, MF, MISource.Value, PFS, IRSlots, Error))
-      return error(Error, MISource.SourceRange);
-    MBB.insert(MBB.end(), MI);
-  }
-  return false;
-}
-
 bool MIRParserImpl::initializeRegisterInfo(MachineFunction &MF,
                                            const yaml::MachineFunction &YamlMF,
                                            PerFunctionMIParsingState &PFS) {

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -83,8 +83,6 @@ public:
                const MachineConstantPool &ConstantPool);
   void convert(ModuleSlotTracker &MST, yaml::MachineJumpTable &YamlJTI,
                const MachineJumpTableInfo &JTI);
-  void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
-               const MachineBasicBlock &MBB);
   void convertStackObjects(yaml::MachineFunction &MF,
                            const MachineFrameInfo &MFI,
                            const TargetRegisterInfo *TRI);
@@ -93,10 +91,6 @@ private:
   void initRegisterMaskIds(const MachineFunction &MF);
 };
 
-} // end namespace llvm
-
-namespace {
-
 /// This class prints out the machine instructions using the MIR serialization
 /// format.
 class MIPrinter {
@@ -112,6 +106,8 @@ public:
       : OS(OS), MST(MST), RegisterMaskIds(RegisterMaskIds),
         StackObjectOperandMapping(StackObjectOperandMapping) {}
 
+  void print(const MachineBasicBlock &MBB);
+
   void print(const MachineInstr &MI);
   void printMBBReference(const MachineBasicBlock &MBB);
   void printIRBlockReference(const BasicBlock &BB);
@@ -125,7 +121,7 @@ public:
   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
 };
 
-} // end anonymous namespace
+} // end namespace llvm
 
 namespace llvm {
 namespace yaml {
@@ -181,11 +177,16 @@ void MIRPrinter::print(const MachineFunction &MF) {
     convert(YamlMF, *ConstantPool);
   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
+  raw_string_ostream StrOS(YamlMF.Body.Value.Value);
+  bool IsNewlineNeeded = false;
   for (const auto &MBB : MF) {
-    yaml::MachineBasicBlock YamlMBB;
-    convert(MST, YamlMBB, MBB);
-    YamlMF.BasicBlocks.push_back(YamlMBB);
+    if (IsNewlineNeeded)
+      StrOS << "\n";
+    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
+        .print(MBB);
+    IsNewlineNeeded = true;
   }
+  StrOS.flush();
   yaml::Output Out(OS);
   Out << YamlMF;
 }
@@ -364,57 +365,6 @@ void MIRPrinter::convert(ModuleSlotTracker &MST,
   }
 }
 
-void MIRPrinter::convert(ModuleSlotTracker &MST,
-                         yaml::MachineBasicBlock &YamlMBB,
-                         const MachineBasicBlock &MBB) {
-  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
-  YamlMBB.ID = (unsigned)MBB.getNumber();
-  if (const auto *BB = MBB.getBasicBlock()) {
-    if (BB->hasName()) {
-      YamlMBB.Name.Value = BB->getName();
-    } else {
-      int Slot = MST.getLocalSlot(BB);
-      if (Slot == -1)
-        YamlMBB.IRBlock.Value = "<badref>";
-      else
-        YamlMBB.IRBlock.Value = (Twine("%ir-block.") + Twine(Slot)).str();
-    }
-  }
-  YamlMBB.Alignment = MBB.getAlignment();
-  YamlMBB.AddressTaken = MBB.hasAddressTaken();
-  YamlMBB.IsLandingPad = MBB.isLandingPad();
-  for (const auto *SuccMBB : MBB.successors()) {
-    std::string Str;
-    raw_string_ostream StrOS(Str);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping)
-        .printMBBReference(*SuccMBB);
-    YamlMBB.Successors.push_back(StrOS.str());
-  }
-  if (MBB.hasSuccessorWeights()) {
-    for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I)
-      YamlMBB.SuccessorWeights.push_back(
-          yaml::UnsignedValue(MBB.getSuccWeight(I)));
-  }
-  // Print the live in registers.
-  const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
-  assert(TRI && "Expected target register info");
-  for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
-    std::string Str;
-    raw_string_ostream StrOS(Str);
-    printReg(*I, StrOS, TRI);
-    YamlMBB.LiveIns.push_back(StrOS.str());
-  }
-  // Print the machine instructions.
-  YamlMBB.Instructions.reserve(MBB.size());
-  std::string Str;
-  for (const auto &MI : MBB) {
-    raw_string_ostream StrOS(Str);
-    MIPrinter(StrOS, MST, RegisterMaskIds, StackObjectOperandMapping).print(MI);
-    YamlMBB.Instructions.push_back(StrOS.str());
-    Str.clear();
-  }
-}
-
 void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
   const auto *TRI = MF.getSubtarget().getRegisterInfo();
   unsigned I = 0;
@@ -422,6 +372,80 @@ void MIRPrinter::initRegisterMaskIds(const MachineFunction &MF) {
     RegisterMaskIds.insert(std::make_pair(Mask, I++));
 }
 
+void MIPrinter::print(const MachineBasicBlock &MBB) {
+  assert(MBB.getNumber() >= 0 && "Invalid MBB number");
+  OS << "bb." << MBB.getNumber();
+  bool HasAttributes = false;
+  if (const auto *BB = MBB.getBasicBlock()) {
+    if (BB->hasName()) {
+      OS << "." << BB->getName();
+    } else {
+      HasAttributes = true;
+      OS << " (";
+      int Slot = MST.getLocalSlot(BB);
+      if (Slot == -1)
+        OS << "<ir-block badref>";
+      else
+        OS << (Twine("%ir-block.") + Twine(Slot)).str();
+    }
+  }
+  if (MBB.hasAddressTaken()) {
+    OS << (HasAttributes ? ", " : " (");
+    OS << "address-taken";
+    HasAttributes = true;
+  }
+  if (MBB.isLandingPad()) {
+    OS << (HasAttributes ? ", " : " (");
+    OS << "landing-pad";
+    HasAttributes = true;
+  }
+  if (MBB.getAlignment()) {
+    OS << (HasAttributes ? ", " : " (");
+    OS << "align " << MBB.getAlignment();
+    HasAttributes = true;
+  }
+  if (HasAttributes)
+    OS << ")";
+  OS << ":\n";
+
+  bool HasLineAttributes = false;
+  // Print the successors
+  if (!MBB.succ_empty()) {
+    OS.indent(2) << "successors: ";
+    for (auto I = MBB.succ_begin(), E = MBB.succ_end(); I != E; ++I) {
+      if (I != MBB.succ_begin())
+        OS << ", ";
+      printMBBReference(**I);
+      if (MBB.hasSuccessorWeights())
+        OS << '(' << MBB.getSuccWeight(I) << ')';
+    }
+    OS << "\n";
+    HasLineAttributes = true;
+  }
+
+  // Print the live in registers.
+  const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();
+  assert(TRI && "Expected target register info");
+  if (!MBB.livein_empty()) {
+    OS.indent(2) << "liveins: ";
+    for (auto I = MBB.livein_begin(), E = MBB.livein_end(); I != E; ++I) {
+      if (I != MBB.livein_begin())
+        OS << ", ";
+      printReg(*I, OS, TRI);
+    }
+    OS << "\n";
+    HasLineAttributes = true;
+  }
+
+  if (HasLineAttributes)
+    OS << "\n";
+  for (const auto &MI : MBB) {
+    OS.indent(2);
+    print(MI);
+    OS << "\n";
+  }
+}
+
 void MIPrinter::print(const MachineInstr &MI) {
   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
   const auto *TRI = SubTarget.getRegisterInfo();

llvm/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir

@@ -15,18 +15,17 @@
 ...
 ---
 name:            trivial_fp_func
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%lr', '%fp', '%lr', '%fp' ]
-    instructions:
-      - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
-      - '%fp = frame-setup ADDXri %sp, 0, 0'
-      # CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
-      - 'frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16'
-      - 'frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8'
-      - 'frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16'
-      - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
-      - '%sp, %fp, %lr = LDPXpost %sp, 2'
-      - RET_ReallyLR
+body: |
+  bb.0.entry:
+    liveins: %lr, %fp, %lr, %fp
+
+    %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
+    %fp = frame-setup ADDXri %sp, 0, 0
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION .cfi_def_cfa %w29, 16
+    frame-setup CFI_INSTRUCTION .cfi_offset %w30, -8
+    frame-setup CFI_INSTRUCTION .cfi_offset %w29, -16
+    BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+    %sp, %fp, %lr = LDPXpost %sp, 2
+    RET_ReallyLR
 ...

llvm/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir

@@ -15,15 +15,14 @@
 ...
 ---
 name:            trivial_fp_func
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%lr', '%fp', '%lr', '%fp' ]
-    instructions:
-      - '%sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2'
-      - '%fp = frame-setup ADDXri %sp, 0, 0'
-      - 'BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp'
-# CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
-      - '%sp, %fp, %lr = LDPXpost %sp, 2'
-      - RET_ReallyLR
+body: |
+  bb.0.entry:
+    liveins: %lr, %fp, %lr, %fp
+
+    %sp = frame-setup STPXpre killed %fp, killed %lr, %sp, -2
+    %fp = frame-setup ADDXri %sp, 0, 0
+    BL @foo, csr_aarch64_aapcs, implicit-def dead %lr, implicit %sp, implicit-def %sp
+  ; CHECK: %sp, %fp, %lr = LDPXpost %sp, 2
+    %sp, %fp, %lr = LDPXpost %sp, 2
+    RET_ReallyLR
 ...

llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir

@@ -38,28 +38,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: [[@LINE+1]]:50: expected the name of the target index
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: [[@LINE+1]]:45: expected the name of the target index
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(0), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...

llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir

@@ -38,28 +38,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: [[@LINE+1]]:50: use of undefined target index 'constdata-start'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: [[@LINE+1]]:45: use of undefined target index 'constdata-start'
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...

llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir

@@ -47,30 +47,29 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start), implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...
 ---
 name:            float2
@@ -79,28 +78,27 @@ liveins:
   - { reg: '%sgpr0_sgpr1' }
 frameInfo:
   maxAlignment:  8
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%sgpr0_sgpr1' ]
-    instructions:
-      - '%sgpr2_sgpr3 = S_GETPC_B64'
-# CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
-      - '%sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc'
-      - '%sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc'
-      - '%sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11'
-      - '%sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc'
-      - '%sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc'
-      - '%sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc'
-      - '%sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc'
-      - '%sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc'
-      - '%sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc'
-      - '%sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0'
-      - '%sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9'
-      - '%sgpr7 = S_MOV_B32 61440'
-      - '%sgpr6 = S_MOV_B32 -1'
-      - '%vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec'
-      - 'BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec'
-      - S_ENDPGM
+body: |
+  bb.0.entry:
+    liveins: %sgpr0_sgpr1
+
+    %sgpr2_sgpr3 = S_GETPC_B64
+  ; CHECK: %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, target-index(amdgpu-constdata-start) + 1, implicit-def %scc, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr3, 0, implicit-def %scc, implicit %scc, implicit-def %scc, implicit %scc
+    %sgpr4_sgpr5 = S_LSHR_B64 %sgpr2_sgpr3, 32, implicit-def dead %scc
+    %sgpr6 = S_LOAD_DWORD_IMM %sgpr0_sgpr1, 11
+    %sgpr7 = S_ASHR_I32 %sgpr6, 31, implicit-def dead %scc
+    %sgpr6_sgpr7 = S_LSHL_B64 %sgpr6_sgpr7, 2, implicit-def dead %scc
+    %sgpr2 = S_ADD_U32 %sgpr2, @float_gv, implicit-def %scc
+    %sgpr3 = S_ADDC_U32 %sgpr4, 0, implicit-def dead %scc, implicit %scc
+    %sgpr4 = S_ADD_U32 %sgpr2, %sgpr6, implicit-def %scc
+    %sgpr5 = S_ADDC_U32 %sgpr3, %sgpr7, implicit-def dead %scc, implicit %scc
+    %sgpr2 = S_LOAD_DWORD_IMM %sgpr4_sgpr5, 0
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 killed %sgpr2, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec
+    S_ENDPGM
 ...

llvm/test/CodeGen/MIR/Generic/basic-blocks.mir

@@ -13,37 +13,37 @@
     ret i32 0
   }
 
+  define i32 @test() {
+  start:
+    ret i32 0
+  }
+
 ...
 ---
-# CHECK: name: foo
+# CHECK-LABEL: name: foo
 # CHECK: body:
-# CHECK-NEXT: - id: 0
-# CHECK-NEXT:   name: entry
-# CHECK-NEXT:   alignment: 0
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: false
+# CHECK-NEXT: bb.0.entry:
 name:            foo
-body:
- - id:           0
-   name:         entry
+body: |
+  bb.0.entry:
 ...
 ---
-# CHECK: name: bar
+# CHECK-LABEL: name: bar
 # CHECK: body:
-# CHECK-NEXT: - id: 0
-# CHECK-NEXT:   name: start
-# CHECK-NEXT:   alignment: 4
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: false
-# CHECK-NEXT: - id: 1
-# CHECK-NEXT:   alignment: 0
-# CHECK-NEXT:   isLandingPad: false
-# CHECK-NEXT:   addressTaken: true
+# CHECK-NEXT: bb.0.start (align 4):
+# CHECK:      bb.1 (address-taken):
 name:            bar
-body:
- - id:           0
-   name:         start
-   alignment:    4
- - id:           1
-   addressTaken: true
+body: |
+  bb.0.start (align 4):
+  bb.1 (address-taken):
+...
+---
+# CHECK-LABEL: name: test
+# CHECK: body:
+# CHECK-NEXT: bb.0.start (address-taken, align 4):
+# CHECK:      bb.1 (address-taken, align 4):
+name:            test
+body: |
+  bb.0.start (align 4, address-taken):
+  bb.1 (address-taken, align 4):
 ...

llvm/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir

@@ -3,14 +3,14 @@
 --- |
 
   define i32 @foo() {
+  entry:
     ret i32 0
   }
 
 ...
 ---
 name:            foo
-body:
- - id:           0
-# CHECK: [[@LINE+1]]:19: expected an IR block reference
-   ir-block:     '0'
+body: |
+  ; CHECK: [[@LINE+1]]:13: expected ':'
+  bb.0.entry
 ...

llvm/test/CodeGen/MIR/Generic/expected-eof-after-successor-mbb.mir

@@ -1,29 +0,0 @@
-# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
-
---- |
-
-  define i32 @foo(i32 %a) {
-  entry:
-    %0 = icmp sle i32 %a, 10
-    br i1 %0, label %less, label %exit
-
-  less:
-    ret i32 0
-
-  exit:
-    ret i32 %a
-  }
-
-...
----
-name:            foo
-body:
-  - id:          0
-    name:        entry
-    # CHECK: [[@LINE+1]]:46: expected end of string after the machine basic block reference
-    successors:  [ '%bb.1.less', '%bb.2.exit 2' ]
-  - id:          1
-    name:        less
-  - id:          2
-    name:        exit
-...

llvm/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir

@@ -17,13 +17,12 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    # CHECK: [[@LINE+1]]:35: expected a machine basic block reference
-    successors:  [ '%bb.1.less', '2' ]
-  - id:          1
-    name:        less
-  - id:          2
-    name:        exit
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:29: expected a machine basic block reference
+    successors: %bb.1.less, 2
+
+  bb.1.less:
+
+  bb.2.exit:
 ...

llvm/test/CodeGen/MIR/Generic/frame-info.mir

@@ -44,9 +44,8 @@ tracksRegLiveness: true
 # CHECK: body
 frameInfo:
   maxAlignment:    4
-body:
-  - id:          0
-    name:        entry
+body: |
+  bb.0.entry:
 ...
 ---
 name:            test2
@@ -84,8 +83,7 @@ frameInfo:
   hasOpaqueSPAdjustment: true
   hasVAStart:      true
   hasMustTailInVarArgFunc: true
-body:
-  - id:          0
-    name:        entry
+body: |
+  bb.0.entry:
 ...
 

llvm/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir

@@ -36,19 +36,18 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-  - id:          1
-    name:        entry
-  - id:          2
-    name:        def
-  - id:          3
-    name:        lbl1
-  - id:          4
-    name:        lbl2
-  - id:          5
-    name:        lbl3
-  - id:          6
-    name:        lbl4
+body: |
+  bb.0.entry:
+
+  bb.1.entry:
+
+  bb.2.def:
+
+  bb.3.lbl1:
+
+  bb.4.lbl2:
+
+  bb.5.lbl3:
+
+  bb.6.lbl4:
 ...

llvm/test/CodeGen/MIR/Generic/llvmIR.mir

@@ -32,6 +32,6 @@
 ...
 ---
 name: foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/llvmIRMissing.mir

@@ -4,6 +4,6 @@
 ---
 # CHECK: name: foo
 name: foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir

@@ -11,9 +11,7 @@
 ...
 ---
 name:            foo
-body:
-# CHECK: id: 0
-# CHECK: ir-block: '%ir-block.0'
- - id:           0
-   ir-block:     '%ir-block.0'
+body: |
+  ; CHECK: bb.0 (%ir-block.0):
+  bb.0 (%ir-block.0):
 ...

llvm/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir

@@ -10,8 +10,9 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: redefinition of machine basic block with id #0
-  - id:       0
-  - id:       0
+body: |
+  ; CHECK: [[@LINE+3]]:3: redefinition of machine basic block with id #0
+  bb.0:
+
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir

@@ -9,8 +9,7 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-# CHECK: [[@LINE+1]]:19: use of undefined IR block '%ir-block.10'
-   ir-block:     '%ir-block.10'
+body: |
+  ; CHECK: [[@LINE+1]]:9: use of undefined IR block '%ir-block.10'
+  bb.0 (%ir-block.10):
 ...

llvm/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir

@@ -12,8 +12,7 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: [[@LINE+2]]:18: basic block 'entrie' is not defined in the function 'foo'
-  - id:          0
-    name:        entrie
+body: |
+  ; CHECK: [[@LINE+1]]:3: basic block 'entrie' is not defined in the function 'foo'
+  bb.0.entrie:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-function.mir

@@ -12,12 +12,12 @@
 ...
 ---
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: function 'faa' isn't defined in the provided LLVM IR
 name:            faa
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function-missing-name.mir

@@ -16,11 +16,11 @@
 ---
 # CHECK: [[@LINE+1]]:1: missing required key 'name'
 nme:             foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 name:            bar
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/machine-function.mir

@@ -27,8 +27,8 @@
 # CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -37,8 +37,8 @@ body:
 # CHECK-NEXT: hasInlineAsm: false
 # CHECK: ...
 name:            bar
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: func
@@ -48,8 +48,8 @@ body:
 # CHECK: ...
 name:            func
 alignment:       8
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: func2
@@ -61,6 +61,6 @@ name:            func2
 alignment:       16
 exposesReturnsTwice: true
 hasInlineAsm:    true
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/Generic/register-info.mir

@@ -22,8 +22,8 @@
 # CHECK-NEXT: tracksSubRegLiveness: false
 # CHECK: ...
 name:            foo
-body:
-  - id: 0
+body: |
+  bb.0:
 ...
 ---
 # CHECK: name: bar
@@ -35,6 +35,6 @@ name: bar
 isSSA: false
 tracksRegLiveness: true
 tracksSubRegLiveness: true
-body:
-  - id: 0
+body: |
+  bb.0:
 ...

llvm/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir

@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: expected a floating point literal
-      - '%1 = FADD_rnf32ri %0, float 3'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: expected a floating point literal
+    %1 = FADD_rnf32ri %0, float 3
+    StoreRetvalF32 %1, 0
+    Return
 ...

llvm/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir

@@ -38,22 +38,20 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
-      - '%3 = FADD_rnf64ri %1, double 3.250000e+00'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
-      - '%6 = FADD_rnf32ri %5, float 6.250000e+00'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %3 = FADD_rnf64ri %1, double 3.250000e+00
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %6 = FADD_rnf32ri %5, float 6.250000e+00
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...
 ---
 name:            test2
@@ -66,20 +64,18 @@ registers:
   - { id: 5, class: float32regs }
   - { id: 6, class: float32regs }
   - { id: 7, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0'
-      - '%1 = CVT_f64_f32 %0, 0'
-      - '%2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1'
-# CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
-      - '%3 = FADD_rnf64ri %1, double 0x7FF8000000000000'
-      - '%4 = CVT_f32_f64 %3, 5'
-      - '%5 = CVT_f32_s32 %2, 5'
-# CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
-      - '%6 = FADD_rnf32ri %5, float 0x7FF8000000000000'
-      - '%7 = FMUL_rnf32rr %6, %4'
-      - 'StoreRetvalF32 %7, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test2_param_0
+    %1 = CVT_f64_f32 %0, 0
+    %2 = LD_i32_avar 0, 4, 1, 0, 32, $test2_param_1
+  ; CHECK: %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %3 = FADD_rnf64ri %1, double 0x7FF8000000000000
+    %4 = CVT_f32_f64 %3, 5
+    %5 = CVT_f32_s32 %2, 5
+  ; CHECK: %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %6 = FADD_rnf32ri %5, float 0x7FF8000000000000
+    %7 = FMUL_rnf32rr %6, %4
+    StoreRetvalF32 %7, 0
+    Return
 ...

llvm/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir

@@ -14,13 +14,11 @@ name:            test
 registers:
   - { id: 0, class: float32regs }
   - { id: 1, class: float32regs }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0'
-# CHECK: [[@LINE+1]]:38: floating point constant does not have type 'float'
-      - '%1 = FADD_rnf32ri %0, float 0xH3C00'
-      - 'StoreRetvalF32 %1, 0'
-      - Return
+body: |
+  bb.0.entry:
+    %0 = LD_f32_avar 0, 4, 1, 2, 32, $test_param_0
+  ; CHECK: [[@LINE+1]]:33: floating point constant does not have type 'float'
+    %1 = FADD_rnf32ri %0, float 0xH3C00
+    StoreRetvalF32 %1, 0
+    Return
 ...

llvm/test/CodeGen/MIR/X86/basic-block-liveins.mir

@@ -9,17 +9,54 @@
     ret i32 %c
   }
 
+  define i32 @test2(i32 %a, i32 %b) {
+  body:
+    %c = add i32 %a, %b
+    ret i32 %c
+  }
+
+  define i32 @test3() {
+  body:
+    ret i32 0
+  }
+
 ...
 ---
 name:            test
-body:
-  # CHECK: name: body
-  # CHECK: liveins: [ '%edi', '%esi' ]
-  # CHECK-NEXT: instructions:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - '%eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _'
-      - 'RETQ %eax'
+body: |
+  ; CHECK-LABEL: bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name:            test2
+body: |
+  ; CHECK-LABEL: name: test2
+  ; Verify that we can have multiple lists of liveins that will be merged into
+  ; one.
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    liveins: %edi, %esi
+  bb.0.body:
+    liveins: %edi
+    liveins: %esi
+
+    %eax = LEA64_32r killed %rdi, 1, killed %rsi, 0, _
+    RETQ %eax
+...
+---
+name:            test3
+body: |
+  ; Verify that we can have an empty list of liveins.
+  ; CHECK-LABEL: name: test3
+  ; CHECK:       bb.0.body:
+  ; CHECK-NEXT:    %eax = MOV32r0 implicit-def dead %eflags
+  bb.0.body:
+    liveins:
+
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
 ...

llvm/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir

@@ -0,0 +1,41 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  ; CHECK: [[@LINE+1]]:8: basic block definition should be located at the start of the line
+  less bb.1:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...

llvm/test/CodeGen/MIR/X86/block-address-operands.mir

@@ -54,84 +54,68 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...
 ---
 name:            test2
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test2, %ir-block."quoted block"), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
 ...
 ---
 name:            slot_in_other_function
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    liveins:         [ '%rdi' ]
-    instructions:
-# CHECK: name: slot_in_other_function
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
-      - 'MOV64mr killed %rdi, 1, _, 0, _, killed %rax'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK-LABEL: name: slot_in_other_function
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr killed %rdi, 1, _, 0, _, killed %rax
+    RETQ
 ...
 ---
 name:            test3
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1' ]
-    instructions:
-# CHECK: name: test3
-# CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1
+  ; CHECK-LABEL: name: test3
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test3, %ir-block.0), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1 (address-taken):
+    RETQ
 ...
 ---
 name:            test4
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-    # CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+  ; CHECK: %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, %ir-block.block) + 2, _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/callee-saved-info.mir

@@ -34,13 +34,12 @@
 ---
 name:            compute
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
 ---
 name:            func
@@ -60,39 +59,37 @@ fixedStack:
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%edi', '%rbx' ]
-    instructions:
-      - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%ebx = COPY %edi'
-      - 'MOV32mr %rsp, 1, _, 12, _, %ebx'
-  - id:          1
-    name:        check
-    successors:  [ '%bb.2.loop', '%bb.3.exit' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - 'CMP32ri8 %ebx, 10, implicit-def %eflags'
-      - 'JG_1 %bb.3.exit, implicit killed %eflags'
-      - 'JMP_1 %bb.2.loop'
-  - id:          2
-    name:        loop
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - '%edi = MOV32rm %rsp, 1, _, 12, _'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%eax = DEC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
-      - 'JMP_1 %bb.1.check'
-  - id:          3
-    name:        exit
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.check
+    liveins: %edi, %rbx
+
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
+    %ebx = COPY %edi
+    MOV32mr %rsp, 1, _, 12, _, %ebx
+
+  bb.1.check:
+    successors: %bb.2.loop, %bb.3.exit
+    liveins: %ebx
+
+    CMP32ri8 %ebx, 10, implicit-def %eflags
+    JG_1 %bb.3.exit, implicit killed %eflags
+    JMP_1 %bb.2.loop
+
+  bb.2.loop:
+    successors: %bb.1.check
+    liveins: %ebx
+
+    %edi = MOV32rm %rsp, 1, _, 12, _
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %eax = DEC32r killed %eax, implicit-def dead %eflags
+    MOV32mr %rsp, 1, _, 12, _, killed %eax
+    JMP_1 %bb.1.check
+
+  bb.3.exit:
+    %eax = MOV32r0 implicit-def dead %eflags
+    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir

@@ -18,14 +18,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 4048'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    CFI_INSTRUCTION .cfi_def_cfa_offset 4048
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 

llvm/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir

@@ -19,15 +19,14 @@ frameInfo:
   stackSize:     8
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rbp' ]
-    instructions:
-      - 'PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
-      - '%rbp = MOV64rr %rsp'
-      # CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
-      - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
+body: |
+  bb.0.entry:
+    liveins: %rbp
+
+    PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    CFI_INSTRUCTION .cfi_offset %rbp, -16
+    %rbp = MOV64rr %rsp
+    ; CHECK: CFI_INSTRUCTION .cfi_def_cfa_register %rbp
+    CFI_INSTRUCTION .cfi_def_cfa_register %rbp
 ...

llvm/test/CodeGen/MIR/X86/cfi-offset.mir

@@ -26,23 +26,22 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    liveins:         [ '%ecx', '%edi', '%edx', '%esi', '%rbx' ]
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
-      - 'CFI_INSTRUCTION .cfi_offset %rbx, -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %ecx, %edi, %edx, %esi, %rbx
+
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: CFI_INSTRUCTION .cfi_offset %rbx, -16
+    CFI_INSTRUCTION .cfi_offset %rbx, -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir

@@ -17,11 +17,9 @@ constants:
 # CHECK: [[@LINE+1]]:18: redefinition of constant pool item '%const.0'
   - id:          0
     value:       'double 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
 ...
 

llvm/test/CodeGen/MIR/X86/constant-pool.mir

@@ -57,17 +57,15 @@ constants:
   - id:          1
     value:       'float 6.250000e+00'
     alignment:   4
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # Verify that alignment can be inferred:
@@ -85,15 +83,13 @@ constants:
     value:       'double 3.250000e+00'
   - id:          1
     value:       'float 6.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # Verify that the non-standard alignments are respected:
@@ -113,17 +109,15 @@ constants:
   - id:          1
     value:       'float 6.250000e+00'
     alignment:   1
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...
 ---
 # CHECK:  name:  test4
@@ -133,15 +127,13 @@ constants:
     value:       'double 3.250000e+00'
   - id:          1
     value:       'float 6.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
-      # CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _'
-      - '%xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _'
-      - '%xmm1 = CVTSS2SDrr killed %xmm1'
-      - '%xmm0 = MULSDrr killed %xmm0, killed %xmm1'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
+    ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
+    %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
+    %xmm1 = CVTSS2SDrr killed %xmm1
+    %xmm0 = MULSDrr killed %xmm0, killed %xmm1
+    RETQ %xmm0
 ...

llvm/test/CodeGen/MIR/X86/constant-value-error.mir

@@ -17,11 +17,9 @@ constants:
   - id:          0
   # CHECK: [[@LINE+1]]:19: expected type
     value:       'dub 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
+    RETQ %xmm0
 ...
 

llvm/test/CodeGen/MIR/X86/dead-register-flag.mir

@@ -15,12 +15,10 @@
 ...
 ---
 name:            foo
-body:
-  # CHECK: name: body
-  - id:          0
-    name:        body
-    instructions:
-      # CHECK: - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  ; CHECK: bb.0.body:
+  bb.0.body:
+    ; CHECK: %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    %eax = IMUL32rri8 %edi, 11, implicit-def dead %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir

@@ -16,14 +16,12 @@ name:            volatile_inc
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:55: duplicate 'volatile' memory operand flag
-      - '%eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:50: duplicate 'volatile' memory operand flag
+    %eax = MOV32rm %rdi, 1, _, 0, _ :: (volatile volatile load 4 from %ir.x)
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    MOV32mr killed %rdi, 1, _, 0, _, %eax :: (volatile store 4 into %ir.x)
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir

@@ -17,22 +17,19 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:36: duplicate 'implicit' register flag
-      - 'JG_1 %bb.2.exit, implicit implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:31: duplicate 'implicit' register flag
+    JG_1 %bb.2.exit, implicit implicit %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %edi
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir

@@ -28,19 +28,18 @@ frameInfo:
   stackSize:     8
   adjustsStack:  true
   hasCalls:      true
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - 'frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 16
-      - '%ecx = COPY %edi'
-      - '%ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags'
-# CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
-      - 'INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di'
-      - '%edi = COPY killed %ecx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%rax = POP64r implicit-def %rsp, implicit %rsp'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %edi, %esi
+
+    frame-setup PUSH64r undef %rax, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    %ecx = COPY %edi
+    %ecx = ADD32rr killed %ecx, killed %esi, implicit-def dead %eflags
+  ; CHECK: INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    INLINEASM $nop, 1, 12, implicit-def dead early-clobber %ax, 12, implicit-def dead early-clobber %di
+    %edi = COPY killed %ecx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %rax = POP64r implicit-def %rsp, implicit %rsp
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir

@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:70: expected 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:65: expected 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, 32)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir

@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:75: expected an integer literal after 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:70: expected an integer literal after 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir

@@ -0,0 +1,40 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  ; CHECK: [[@LINE+1]]:3: expected a basic block definition before instructions
+  successors: %bb.1.less, %bb.2.exit
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...

llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir

@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:56: expected an IR block reference
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@test, _), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:51: expected an IR block reference
+    %rax = LEA64r %rip, 1, _, blockaddress(@test, _), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir

@@ -24,21 +24,19 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: [[@LINE+1]]:43: expected ','
-      - 'CFI_INSTRUCTION .cfi_offset %rbx -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:38: expected ','
+    CFI_INSTRUCTION .cfi_offset %rbx -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir

@@ -16,12 +16,10 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry2
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:92: expected ',' before the next machine memory operand
-      - 'INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)'
-      - RETQ
+body: |
+  bb.0.entry2:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand
+    INC32m killed %rdi, 1, _, 0, _, implicit-def dead %eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir

@@ -19,20 +19,16 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
-     - 'JG_1 %bb.2.exit, implicit %eax'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
+    JG_1 %bb.2.exit, implicit %eax
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir

@@ -19,20 +19,16 @@
 ...
 ---
 name:            foo
-body:
- - id:              0
-   name:            entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-# CHECK: [[@LINE+1]]:26: expected an implicit register operand 'implicit %eflags'
-     - 'JG_1 %bb.2.exit, implicit-def %eflags'
- - id:              1
-   name:            less
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id:              2
-   name:            exit
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+  ; CHECK: [[@LINE+1]]:22: expected an implicit register operand 'implicit %eflags'
+    JG_1 %bb.2.exit, implicit-def %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.exit:
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir

@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:60: expected 'from'
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:55: expected 'from'
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a)
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir

@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:49: expected an IR function reference
-      - '%rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:44: expected an IR function reference
+    %rax = LEA64r %rip, 1, _, blockaddress(@addr, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir

@@ -17,18 +17,14 @@
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.block' ]
-    instructions:
-      # CHECK: [[@LINE+1]]:49: expected a global value
-      - '%rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _'
-      - 'MOV64mr %rip, 1, _, @addr, _, killed %rax'
-      - 'JMP64m %rip, 1, _, @addr, _'
-  - id:              1
-    name:            block
-    addressTaken:    true
-    instructions:
-      - RETQ
+body: |
+  bb.0.entry:
+    successors: %bb.1.block
+    ; CHECK: [[@LINE+1]]:44: expected a global value
+    %rax = LEA64r %rip, 1, _, blockaddress(0, %ir-block.block), _
+    MOV64mr %rip, 1, _, @addr, _, killed %rax
+    JMP64m %rip, 1, _, @addr, _
+
+  bb.1.block (address-taken):
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir

@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:42: expected an integer literal after '+'
-      - '%rax = MOV64rm %rip, 1, _, @G + , _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:37: expected an integer literal after '+'
+    %rax = MOV64rm %rip, 1, _, @G + , _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir

@@ -0,0 +1,38 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:
+    ret i32 0
+
+  exit:
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:29: expected an integer literal after '('
+    successors: %bb.1.less (_), %bb.2.exit(32)
+    liveins: %edi
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...

llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir

@@ -14,12 +14,10 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:53: expected 'load' or 'store' memory operation
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:48: expected 'load' or 'store' memory operation
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (4 from %ir.a)
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-machine-operand.mir

@@ -10,12 +10,10 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:24: expected a machine operand
-     - '%eax = XOR32rr ='
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:20: expected a machine operand
+    %eax = XOR32rr =
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir

@@ -48,14 +48,12 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:51: expected a metadata node after 'debug-location'
-      - 'DBG_VALUE _, 0, !12, !13, debug-location 14'
-      - 'MOV32mr %stack.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:46: expected a metadata node after 'debug-location'
+    DBG_VALUE _, 0, !12, !13, debug-location 14
+    MOV32mr %stack.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir

@@ -48,14 +48,12 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:33: expected metadata id after '!'
-      - 'DBG_VALUE _, 0, !12, ! _'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:28: expected metadata id after '!'
+    DBG_VALUE _, 0, !12, ! _
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir

@@ -17,14 +17,13 @@ registers:
   # CHECK: [[@LINE+1]]:48: expected a named register
   - { id: 1, class: gr32, preferred-register: '%0' }
   - { id: 2, class: gr32, preferred-register: '%edi' }
-body:
-  - id:              0
-    name:            body
-    liveins:         [ '%edi', '%esi' ]
-    instructions:
-      - '%1 = COPY %esi'
-      - '%2 = COPY %edi'
-      - '%2 = IMUL32rr %2, %1, implicit-def dead %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %1 = COPY %esi
+    %2 = COPY %edi
+    %2 = IMUL32rr %2, %1, implicit-def dead %eflags
+    %eax = COPY %2
+    RETQ killed %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir

@@ -32,13 +32,12 @@
 ---
 name:            compute
 tracksRegLiveness: true
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...
 ---
 name:            func
@@ -53,39 +52,37 @@ fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%0' }
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%edi', '%rbx' ]
-    instructions:
-      - 'frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - '%rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%ebx = COPY %edi'
-      - 'MOV32mr %rsp, 1, _, 12, _, %ebx'
-  - id:          1
-    name:        check
-    successors:  [ '%bb.2.loop', '%bb.3.exit' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - 'CMP32ri8 %ebx, 10, implicit-def %eflags'
-      - 'JG_1 %bb.3.exit, implicit killed %eflags'
-      - 'JMP_1 %bb.2.loop'
-  - id:          2
-    name:        loop
-    successors:  [ '%bb.1.check' ]
-    liveins:     [ '%ebx' ]
-    instructions:
-      - '%edi = MOV32rm %rsp, 1, _, 12, _'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%eax = DEC32r killed %eax, implicit-def dead %eflags'
-      - 'MOV32mr %rsp, 1, _, 12, _, killed %eax'
-      - 'JMP_1 %bb.1.check'
-  - id:          3
-    name:        exit
-    instructions:
-      - '%eax = MOV32r0 implicit-def dead %eflags'
-      - '%rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.check
+    liveins: %edi, %rbx
+
+    frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
+    %ebx = COPY %edi
+    MOV32mr %rsp, 1, _, 12, _, %ebx
+
+  bb.1.check:
+    successors: %bb.2.loop, %bb.3.exit
+    liveins: %ebx
+
+    CMP32ri8 %ebx, 10, implicit-def %eflags
+    JG_1 %bb.3.exit, implicit killed %eflags
+    JMP_1 %bb.2.loop
+
+  bb.2.loop:
+    successors: %bb.1.check
+    liveins: %ebx
+
+    %edi = MOV32rm %rsp, 1, _, 12, _
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %eax = DEC32r killed %eax, implicit-def dead %eflags
+    MOV32mr %rsp, 1, _, 12, _, killed %eax
+    JMP_1 %bb.1.check
+
+  bb.3.exit:
+    %eax = MOV32r0 implicit-def dead %eflags
+    %rsp = ADD64ri8 %rsp, 16, implicit-def dead %eflags
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir

@@ -17,12 +17,11 @@ registers:
 liveins:
   # CHECK: [[@LINE+1]]:13: expected a named register
   - { reg: '%0' }
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-named-register-livein.mir

@@ -10,12 +10,11 @@
 ...
 ---
 name:            test
-body:
-  - id:          0
-    name:        body
-    # CHECK: [[@LINE+1]]:21: expected a named register
-    liveins:     [ '%0' ]
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    ; CHECK: [[@LINE+1]]:14: expected a named register
+    liveins: %0
+
+    %eax = COPY %edi
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir

@@ -0,0 +1,41 @@
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+
+--- |
+
+  define i32 @foo(i32 %a) {
+  entry:
+    %0 = icmp sle i32 %a, 10
+    br i1 %0, label %less, label %exit
+
+  less:                                             ; preds = %entry
+    ret i32 0
+
+  exit:                                             ; preds = %entry
+    ret i32 %a
+  }
+
+...
+---
+name:            foo
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+  ; CHECK: [[@LINE+1]]:19: expected line break at the end of a list
+    liveins: %edi 44
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit killed %eflags
+
+  bb.1.less:
+    %eax = MOV32r0 implicit-def dead %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    liveins: %edi
+
+    %eax = COPY killed %edi
+    RETQ killed %eax
+...

llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir

@@ -18,20 +18,16 @@
 ...
 ---
 name:            foo
-body:
- - id: 0
-   name:   entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
-     - 'JG_1 %bb.nah, implicit %eflags'
- - id: 1
-   name: yes
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 2
-   name: nah
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:14: expected a number after '%bb.'
+    JG_1 %bb.nah, implicit %eflags
+
+  bb.1.true:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2.nah:
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir

@@ -16,14 +16,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: [[@LINE+1]]:46: expected a cfi offset
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset _'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: [[@LINE+1]]:41: expected a cfi offset
+    CFI_INSTRUCTION .cfi_def_cfa_offset _
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 

llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir

@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:65: expected a pointer IR value
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:60: expected a pointer IR value
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from %ir.b)
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir

@@ -16,17 +16,15 @@ name:            memory_alignment
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:76: expected an integer literal after 'align'
-      - '%xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)'
-      - '%xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)'
-      - '%xmm2 = FsFLD0SS'
-      - '%xmm1 = MOVSSrr killed %xmm1, killed %xmm2'
-      - 'MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)'
-      - 'MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)'
-      - RETQ
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:71: expected an integer literal after 'align'
+    %xmm0 = MOVAPSrm %rdi, 1, _, 0, _ :: (load 16 from %ir.vec, align -32)
+    %xmm1 = MOVAPSrm %rdi, 1, _, 16, _ :: (load 16 from %ir.vec + 16, align 32)
+    %xmm2 = FsFLD0SS
+    %xmm1 = MOVSSrr killed %xmm1, killed %xmm2
+    MOVAPSmr %rdi, 1, _, 0, _, killed %xmm0 :: (store 16 into %ir.vec, align 32)
+    MOVAPSmr killed %rdi, 1, _, 16, _, killed %xmm1 :: (store 16 into %ir.vec + 16, align 32)
+    RETQ
 ...

llvm/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir

@@ -24,21 +24,19 @@ frameInfo:
   hasCalls:        true
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp'
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 16'
-      # CHECK: [[@LINE+1]]:38: expected a cfi register
-      - 'CFI_INSTRUCTION .cfi_offset %0, -16'
-      - '%ebx = COPY %edi, implicit-def %rbx'
-      - '%ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags'
-      - '%ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags'
-      - '%edi = COPY %ebx'
-      - 'CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp'
-      - '%eax = LEA64_32r killed %rbx, 1, %rbx, 0, _'
-      - '%rbx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 16
+    ; CHECK: [[@LINE+1]]:33: expected a cfi register
+    CFI_INSTRUCTION .cfi_offset %0, -16
+    %ebx = COPY %edi, implicit-def %rbx
+    %ebx = ADD32rr %ebx, killed %esi, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %edx, implicit-def dead %eflags
+    %ebx = ADD32rr %ebx, killed %ecx, implicit-def dead %eflags
+    %edi = COPY %ebx
+    CALL64pcrel32 @foo, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp
+    %eax = LEA64_32r killed %rbx, 1, %rbx, 0, _
+    %rbx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-register-after-flags.mir

@@ -12,11 +12,9 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK: [[@LINE+1]]:37: expected a register after register flags
-     - '%eax = MOV32r0 implicit-def 2'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:33: expected a register after register flags
+    %eax = MOV32r0 implicit-def 2
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir

@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:58: expected the size integer literal after memory operation
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:53: expected the size integer literal after memory operation
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load from %ir.a)
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir

@@ -16,14 +16,12 @@ registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr8 }
   - { id: 2, class: gr8 }
-body:
-  - name:        entry
-    id:          0
-    instructions:
-      - '%0 = COPY %edi'
-      # CHECK: [[@LINE+1]]:25: expected a subregister index after ':'
-      - '%1 = COPY %0 : 42'
-      - '%2 = AND8ri %1, 1, implicit-def %eflags'
-      - '%al = COPY %2'
-      - 'RETQ %al'
+body: |
+  bb.0.entry:
+    %0 = COPY %edi
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
+    %1 = COPY %0 : 42
+    %2 = AND8ri %1, 1, implicit-def %eflags
+    %al = COPY %2
+    RETQ %al
 ...

llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir

@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: [[@LINE+1]]:51: expected the name of the target flag
-      - '%rax = MOV64rm %rip, 1, _, target-flags( ) @G, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:46: expected the name of the target flag
+    %rax = MOV64rm %rip, 1, _, target-flags( ) @G, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir

@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:65: expected an IR value reference
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:60: expected an IR value reference
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 from a)
+    RETQ %eax
 ...
 

llvm/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir

@@ -17,12 +17,11 @@ registers:
 liveins:
   # CHECK: [[@LINE+1]]:34: expected a virtual register
   - { reg: '%edi', virtual-reg: '%edi' }
-body:
-  - id:          0
-    name:        body
-    liveins:     [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi
+
+    %0 = COPY %edi
+    %eax = COPY %0
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir

@@ -29,38 +29,36 @@
 ---
 name:            test
 tracksRegLiveness: true
-body:
-  - id:              0
-    name:            entry
-    successors:      [ '%bb.1.entry', '%bb.2.entry' ]
-    liveins:         [ '%edi' ]
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 520, implicit-def %eflags'
-      - '%rcx = LOAD_STACK_GUARD'
-      - 'MOV64mr %rsp, 1, _, 512, _, %rcx'
-      - '%rax = MOVSX64rr32 %edi'
-      - '%eax = MOV32rm %rsp, 4, %rax, 0, _'
-      - 'CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags'
-      - 'JNE_1 %bb.2.entry, implicit %eflags'
-  - id:              1
-    name:            entry
-    liveins:         [ '%eax' ]
-    instructions:
-      - '%rsp = ADD64ri32 %rsp, 520, implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:              2
-    name:            entry
-    instructions:
-      # CHECK:      CALL64pcrel32 $__stack_chk_fail,
-      # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
-      # CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
-      # CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
-      # CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
-      # CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
-      - 'CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp'
-      - 'CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp'
+body: |
+  bb.0.entry:
+    successors: %bb.1.entry, %bb.2.entry
+    liveins: %edi
+
+    %rsp = SUB64ri32 %rsp, 520, implicit-def %eflags
+    %rcx = LOAD_STACK_GUARD
+    MOV64mr %rsp, 1, _, 512, _, %rcx
+    %rax = MOVSX64rr32 %edi
+    %eax = MOV32rm %rsp, 4, %rax, 0, _
+    CMP64rm %rcx, %rsp, 1, _, 512, _, implicit-def %eflags
+    JNE_1 %bb.2.entry, implicit %eflags
+
+  bb.1.entry:
+    liveins: %eax
+
+    %rsp = ADD64ri32 %rsp, 520, implicit-def %eflags
+    RETQ %eax
+
+  bb.2.entry:
+    ; CHECK:      CALL64pcrel32 $__stack_chk_fail,
+    ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail.09-_,
+    ; CHECK-NEXT: CALL64pcrel32 $"__stack_chk_fail$",
+    ; CHECK-NEXT: CALL64pcrel32 $"$Quoted \09 External symbol \11 ",
+    ; CHECK-NEXT: CALL64pcrel32 $__stack_chk_fail + 2,
+    ; CHECK-NEXT: CALL64pcrel32 $" check stack - 20" - 20,
+    CALL64pcrel32 $__stack_chk_fail, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail.09-_, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail$, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $"$Quoted \09 External symbol \11 ", csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $__stack_chk_fail + 2, csr_64, implicit %rsp, implicit-def %rsp
+    CALL64pcrel32 $" check stack - 20" - 20, csr_64, implicit %rsp, implicit-def %rsp
 ...

llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir

@@ -26,16 +26,14 @@ fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true }
 stack:
   - { id: 0, name: b, offset: -8, size: 4, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - 'frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp'
-      - CFI_INSTRUCTION .cfi_def_cfa_offset 8
-# CHECK: name: test
-# CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
-      - '%eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)'
-      - 'MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)'
-      - '%edx = POP32r implicit-def %esp, implicit %esp'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    frame-setup PUSH32r undef %eax, implicit-def %esp, implicit %esp
+    CFI_INSTRUCTION .cfi_def_cfa_offset 8
+  ; CHECK: name: test
+  ; CHECK: %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+    %eax = MOV32rm %esp, 1, _, 8, _ :: (load 4 from %fixed-stack.0, align 16)
+    MOV32mr %esp, 1, _, 0, _, %eax :: (store 4 into %ir.b)
+    %edx = POP32r implicit-def %esp, implicit %esp
+    RETL %eax
 ...

llvm/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir

@@ -20,11 +20,9 @@ fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 # CHECK: [[@LINE+1]]:11: redefinition of fixed stack object '%fixed-stack.0'
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%eax = MOV32rm %esp, 1, _, 4, _'
-      - '%eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %esp, 1, _, 4, _
+    %eax = ADD32rm killed %eax, %esp, 1, _, 8, _, implicit-def dead %eflags
+    RETL %eax
 ...

llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir

@@ -25,11 +25,9 @@ fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 4, isImmutable: true, isAliased: false }
 stack:
   - { id: 0, offset: -8, size: 4, alignment: 4 }
-body:
-  - id:          0
-    name:        entry
-    instructions:
-      - '%eax = MOV32rm %esp, 1, _, 8, _'
-      - 'MOV32mr %esp, 1, _, 0, _, %eax'
-      - 'RETL %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %esp, 1, _, 8, _
+    MOV32mr %esp, 1, _, 0, _, %eax
+    RETL %eax
 ...

llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir

@@ -40,33 +40,34 @@ frameInfo:
   restorePoint:  '%bb.2.true'
 stack:
   - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }
-body:
-  - id:          0
-    successors:  [ '%bb.2.true', '%bb.1' ]
-    liveins:     [ '%edi', '%esi' ]
-    instructions:
-      - '%eax = COPY %edi'
-      - 'CMP32rr %eax, killed %esi, implicit-def %eflags'
-      - 'JL_1 %bb.2.true, implicit killed %eflags'
-  - id:          1
-    successors:  [ '%bb.3.false' ]
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'JMP_1 %bb.3.false'
-  - id:          2
-    name:        'true'
-    successors:  [ '%bb.3.false' ]
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax'
-      - 'ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
-      - '%rsi = LEA64r %stack.0.tmp, 1, _, 0, _'
-      - '%edi = MOV32r0 implicit-def dead %eflags'
-      - 'CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax'
-      - 'ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp'
-  - id:          3
-    name:        'false'
-    liveins:     [ '%eax' ]
-    instructions:
-      - 'RETQ %eax'
+body: |
+  bb.0:
+    successors: %bb.2.true, %bb.1
+    liveins: %edi, %esi
+
+    %eax = COPY %edi
+    CMP32rr %eax, killed %esi, implicit-def %eflags
+    JL_1 %bb.2.true, implicit killed %eflags
+
+  bb.1:
+    successors: %bb.3.false
+    liveins: %eax
+
+    JMP_1 %bb.3.false
+
+  bb.2.true:
+    successors: %bb.3.false
+    liveins: %eax
+
+    MOV32mr %stack.0.tmp, 1, _, 0, _, killed %eax
+    ADJCALLSTACKDOWN64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
+    %rsi = LEA64r %stack.0.tmp, 1, _, 0, _
+    %edi = MOV32r0 implicit-def dead %eflags
+    CALL64pcrel32 @doSomething, csr_64, implicit %rsp, implicit %edi, implicit %rsi, implicit-def %rsp, implicit-def %eax
+    ADJCALLSTACKUP64 0, 0, implicit-def %rsp, implicit-def dead %eflags, implicit %rsp
+
+  bb.3.false:
+    liveins: %eax
+
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir

@@ -18,22 +18,18 @@
 ...
 ---
 name:            compute
-body:
-  - name:        body
-    id:          0
-    instructions:
-      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    %eax = IMUL32rri8 %edi, 11, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            foo
-body:
-  - name:        entry
-    id:          0
-    instructions:
-      # CHECK: frame-setup PUSH64r %rax
-      - 'frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp'
-      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
-      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: frame-setup PUSH64r %rax
+    frame-setup PUSH64r %rax, implicit-def %rsp, implicit %rsp
+    CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax
+    %rdx = POP64r implicit-def %rsp, implicit %rsp
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/function-liveins.mir

@@ -25,14 +25,13 @@ registers:
 liveins:
   - { reg: '%edi', virtual-reg: '%0' }
   - { reg: '%esi', virtual-reg: '%1' }
-body:
-  - id:              0
-    name:            body
-    liveins:         [ '%edi', '%esi' ]
-    instructions:
-      - '%1 = COPY %esi'
-      - '%0 = COPY %edi'
-      - '%2 = ADD32rr %0, %1, implicit-def dead %eflags'
-      - '%eax = COPY %2'
-      - 'RETQ %eax'
+body: |
+  bb.0.body:
+    liveins: %edi, %esi
+
+    %1 = COPY %esi
+    %0 = COPY %edi
+    %2 = ADD32rr %0, %1, implicit-def dead %eflags
+    %eax = COPY %2
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/global-value-operands.mir

@@ -62,91 +62,79 @@
 ---
 # CHECK: name: inc
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: - '%rax = MOV64rm %rip, 1, _, @G, _'
-      - '%rax = MOV64rm %rip, 1, _, @G, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: %rax = MOV64rm %rip, 1, _, @G, _
+    %rax = MOV64rm %rip, 1, _, @G, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 # CHECK: name: inc2
 name: inc2
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: - '%rax = MOV64rm %rip, 1, _, @0, _'
-      - '%rax = MOV64rm %rip, 1, _, @0, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: %rax = MOV64rm %rip, 1, _, @0, _
+    %rax = MOV64rm %rip, 1, _, @0, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...
 ---
 name:            test
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @".$0",
-      # CHECK: , @-_-,
-      # CHECK: , @_-_a,
-      # CHECK: , @"$.-B",
-      - '%rax = MOV64rm %rip, 1, _, @.$0, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @-_-, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'
-      - '%rax = MOV64rm %rip, 1, _, @_-_a, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @$.-B, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @".$0",
+    ; CHECK: , @-_-,
+    ; CHECK: , @_-_a,
+    ; CHECK: , @"$.-B",
+    %rax = MOV64rm %rip, 1, _, @.$0, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @-_-, _
+    MOV32mr killed %rcx, 1, _, 0, _, killed %eax
+    %rax = MOV64rm %rip, 1, _, @_-_a, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @$.-B, _
+    MOV32mr killed %rcx, 1, _, 0, _, %eax
+    RETQ %eax
 ...
 ---
 name:            test2
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @"\01Hello@$%09 \5C World,",
-      - '%rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @"\01Hello@$%09 \5C World,",
+    %rax = MOV64rm %rip, 1, _, @"\01Hello@$%09 \\ World,", _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    RETQ %eax
 ...
 ---
 # CHECK: name: test3
 name:            test3
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      # CHECK: , @".$0",
-      # CHECK: , @-_-,
-      # CHECK: , @_-_a + 4,
-      # CHECK: , @"$.-B" - 8,
-      - '%rax = MOV64rm %rip, 1, _, @.$0 + 0, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @-_- - 0, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, killed %eax'
-      - '%rax = MOV64rm %rip, 1, _, @_-_a + 4, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%rcx = MOV64rm %rip, 1, _, @$.-B - 8, _'
-      - 'MOV32mr killed %rcx, 1, _, 0, _, %eax'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: , @".$0",
+    ; CHECK: , @-_-,
+    ; CHECK: , @_-_a + 4,
+    ; CHECK: , @"$.-B" - 8,
+    %rax = MOV64rm %rip, 1, _, @.$0 + 0, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @-_- - 0, _
+    MOV32mr killed %rcx, 1, _, 0, _, killed %eax
+    %rax = MOV64rm %rip, 1, _, @_-_a + 4, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %rcx = MOV64rm %rip, 1, _, @$.-B - 8, _
+    MOV32mr killed %rcx, 1, _, 0, _, %eax
+    RETQ %eax
 ...
 ---
 # CHECK: name: tf
 name: tf
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
-      - '%rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax, implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
+    %rax = MOV64rm %rip, 1, _, target-flags(x86-gotpcrel) @G, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax, implicit-def %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/immediate-operands.mir

@@ -17,24 +17,20 @@
 ---
 # CHECK: name: foo
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32ri 42'
-     # CHECK-NEXT: - 'RETQ %eax'
-     - '%eax = MOV32ri 42'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32ri 42
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32ri 42
+    RETQ %eax
 ...
 ---
 # CHECK: name: bar
 name:            bar
-body:
- - id:           0
-   name:         entry
-   instructions:
-     # CHECK:      - '%eax = MOV32ri -11'
-     # CHECK-NEXT: - 'RETQ %eax'
-     - '%eax = MOV32ri -11'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK:      %eax = MOV32ri -11
+    ; CHECK-NEXT: RETQ %eax
+    %eax = MOV32ri -11
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/implicit-register-flag.mir

@@ -19,24 +19,20 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      # CHECK:      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      # CHECK-NEXT: - 'JG_1 %bb.2.exit, implicit %eflags'
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      # CHECK: - '%eax = MOV32r0 implicit-def %eflags'
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      - '%eax = COPY %edi'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+    ; CHECK:      CMP32ri8 %edi, 10, implicit-def %eflags
+    ; CHECK-NEXT: JG_1 %bb.2.exit, implicit %eflags
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+
+  bb.1.less:
+    ; CHECK: %eax = MOV32r0 implicit-def %eflags
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.2.exit:
+    %eax = COPY %edi
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir

@@ -59,19 +59,17 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:           0
-    name:         entry
-    liveins:      [ '%edi' ]
-    instructions:
-      # CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
-      # CHECK: %eax = COPY %0, debug-location !15
-      # CHECK: RETQ %eax, debug-location !15
-      - '%0 = COPY %edi'
-      - 'DBG_VALUE debug-use _, 0, !12, !13, debug-location !14'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0, debug-location !15'
-      - 'RETQ %eax, debug-location !15'
+body: |
+  bb.0.entry:
+    liveins: %edi
+    ; CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
+    ; CHECK: %eax = COPY %0, debug-location !15
+    ; CHECK: RETQ %eax, debug-location !15
+    %0 = COPY %edi
+    DBG_VALUE debug-use _, 0, !12, !13, debug-location !14
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0, debug-location !15
+    RETQ %eax, debug-location !15
 ...
 ---
 name:            test_typed_immediates
@@ -83,19 +81,18 @@ frameInfo:
   maxAlignment:  4
 stack:
   - { id: 0, name: x.addr, size: 4, alignment: 4 }
-body:
-  - id:           0
-    name:         entry
-    liveins:      [ '%edi' ]
-    instructions:
-      - '%0 = COPY %edi'
-# CHECK:      DBG_VALUE _, i32 0, !12, !13
-# CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13
-# CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
-      - 'DBG_VALUE _, i32 0, !12, !13'
-      - 'DBG_VALUE _, i64 -22, !12, !13'
-      - 'DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13'
-      - 'MOV32mr %stack.0.x.addr, 1, _, 0, _, %0'
-      - '%eax = COPY %0'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %edi
+
+    %0 = COPY %edi
+  ; CHECK:      DBG_VALUE _, i32 0, !12, !13
+  ; CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13
+  ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
+    DBG_VALUE _, i32 0, !12, !13
+    DBG_VALUE _, i64 -22, !12, !13
+    DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13
+    MOV32mr %stack.0.x.addr, 1, _, 0, _, %0
+    %eax = COPY %0
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir

@@ -16,12 +16,10 @@ name:            test
 constants:
   - id:          0
     value:       'double 3.250000e+00'
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:52: use of undefined constant '%const.10'
-      - '%xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _'
-      - 'RETQ %xmm0'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:47: use of undefined constant '%const.10'
+    %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.10, _
+    RETQ %xmm0
 ...
 

llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir

@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-# CHECK: [[@LINE+1]]:50: use of undefined target flag 'x86-test'
-      - '%rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _'
-      - '%eax = MOV32rm killed %rax, 1, _, 0, _'
-      - '%eax = INC32r killed %eax, implicit-def dead %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:45: use of undefined target flag 'x86-test'
+    %rax = MOV64rm %rip, 1, _, target-flags(x86-test) @G, _
+    %eax = MOV32rm killed %rax, 1, _, 0, _
+    %eax = INC32r killed %eax, implicit-def dead %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/jump-table-info.mir

@@ -68,48 +68,41 @@ jumpTable:
   entries:
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-    # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:          2
-    name:        def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          3
-    name:        lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:          4
-    name:        lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:          5
-    name:        lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:          6
-    name:        lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...
 ---
 name:            test_jumptable2
@@ -118,47 +111,40 @@ jumpTable:
   entries:
     - id:        1
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-    # Verify that the printer will use an id of 0 for this jump table:
-    # CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.1, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:         2
-    name:       def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:         3
-    name:       lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:         4
-    name:       lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:         5
-    name:       lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:         6
-    name:       lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+    ; Verify that the printer will use an id of 0 for this jump table:
+    ; CHECK: %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rcx = LEA64r %rip, 1, _, %jump-table.1, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir

@@ -38,45 +38,39 @@ jumpTable:
 # CHECK: [[@LINE+1]]:18: redefinition of jump table entry '%jump-table.0'
     - id:        0
       blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.2.def', '%bb.1.entry' ]
-    instructions:
-      - '%eax = MOV32rr %edi, implicit-def %rax'
-      - 'CMP32ri8 %edi, 3, implicit-def %eflags'
-      - 'JA_1 %bb.2.def, implicit %eflags'
-  - id:          1
-    name:        entry
-    successors:  [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
-    instructions:
-      - '%rcx = LEA64r %rip, 1, _, %jump-table.0, _'
-      - '%rax = MOVSX64rm32 %rcx, 4, %rax, 0, _'
-      - '%rax = ADD64rr %rax, %rcx, implicit-def %eflags'
-      - 'JMP64r %rax'
-  - id:          2
-    name:        def
-    instructions:
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ %eax'
-  - id:          3
-    name:        lbl1
-    instructions:
-      - '%eax = MOV32ri 1'
-      - 'RETQ %eax'
-  - id:          4
-    name:        lbl2
-    instructions:
-      - '%eax = MOV32ri 2'
-      - 'RETQ %eax'
-  - id:          5
-    name:        lbl3
-    instructions:
-      - '%eax = MOV32ri 4'
-      - 'RETQ %eax'
-  - id:          6
-    name:        lbl4
-    instructions:
-      - '%eax = MOV32ri 8'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.2.def, %bb.1.entry
+
+    %eax = MOV32rr %edi, implicit-def %rax
+    CMP32ri8 %edi, 3, implicit-def %eflags
+    JA_1 %bb.2.def, implicit %eflags
+
+  bb.1.entry:
+    successors: %bb.3.lbl1, %bb.4.lbl2, %bb.5.lbl3, %bb.6.lbl4
+
+    %rcx = LEA64r %rip, 1, _, %jump-table.0, _
+    %rax = MOVSX64rm32 %rcx, 4, %rax, 0, _
+    %rax = ADD64rr %rax, %rcx, implicit-def %eflags
+    JMP64r %rax
+
+  bb.2.def:
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ %eax
+
+  bb.3.lbl1:
+    %eax = MOV32ri 1
+    RETQ %eax
+
+  bb.4.lbl2:
+    %eax = MOV32ri 2
+    RETQ %eax
+
+  bb.5.lbl3:
+    %eax = MOV32ri 4
+    RETQ %eax
+
+  bb.6.lbl4:
+    %eax = MOV32ri 8
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/killed-register-flag.mir

@@ -19,25 +19,22 @@
 ...
 ---
 name:            foo
-body:
-  - id:          0
-    name:        entry
-    successors:  [ '%bb.1.less', '%bb.2.exit' ]
-    instructions:
-      - 'CMP32ri8 %edi, 10, implicit-def %eflags'
-      - 'JG_1 %bb.2.exit, implicit %eflags'
-  - id:          1
-    name:        less
-    instructions:
-      # CHECK:      - '%eax = MOV32r0
-      # CHECK-NEXT: - 'RETQ killed %eax
-      - '%eax = MOV32r0 implicit-def %eflags'
-      - 'RETQ killed %eax'
-  - id:          2
-    name:        exit
-    instructions:
-      # CHECK:      - '%eax = COPY killed %edi
-      # CHECK-NEXT: - 'RETQ killed %eax
-      - '%eax = COPY killed %edi'
-      - 'RETQ killed %eax'
+body: |
+  bb.0.entry:
+    successors: %bb.1.less, %bb.2.exit
+
+    CMP32ri8 %edi, 10, implicit-def %eflags
+    JG_1 %bb.2.exit, implicit %eflags
+
+  bb.1.less:
+    ; CHECK:      %eax = MOV32r0
+    ; CHECK-NEXT: RETQ killed %eax
+    %eax = MOV32r0 implicit-def %eflags
+    RETQ killed %eax
+
+  bb.2.exit:
+    ; CHECK:      %eax = COPY killed %edi
+    ; CHECK-NEXT: RETQ killed %eax
+    %eax = COPY killed %edi
+    RETQ killed %eax
 ...

llvm/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir

@@ -16,14 +16,12 @@ frameInfo:
   stackSize:       4040
 stack:
   - { id: 0, name: tmp, offset: -4176, size: 4168, alignment: 4 }
-body:
-  - id:              0
-    name:            entry
-    instructions:
-      - '%rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags'
-     # CHECK: [[@LINE+1]]:46: expected a 32 bit integer (the cfi offset is too large)
-      - 'CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456'
-      - '%rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags'
-      - 'RETQ'
+body: |
+  bb.0.entry:
+    %rsp = SUB64ri32 %rsp, 4040, implicit-def dead %eflags
+    ; CHECK: [[@LINE+1]]:41: expected a 32 bit integer (the cfi offset is too large)
+    CFI_INSTRUCTION .cfi_def_cfa_offset 123456789123456
+    %rsp = ADD64ri32 %rsp, 4040, implicit-def dead %eflags
+    RETQ
 ...
 

llvm/test/CodeGen/MIR/X86/large-immediate-operand-error.mir

@@ -10,11 +10,9 @@
 ...
 ---
 name:            foo
-body:
- - id:           0
-   name:         entry
-   instructions:
-# CHECK: [[@LINE+1]]:24: integer literal is too large to be an immediate operand
-     - '%eax = MOV32ri 12346127502983478823754212949184914'
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+  ; CHECK: [[@LINE+1]]:20: integer literal is too large to be an immediate operand
+    %eax = MOV32ri 12346127502983478823754212949184914
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/large-index-number-error.mir

@@ -18,18 +18,16 @@
 ...
 ---
 name:            foo
-body:
- - id: 0
-   name: entry
-   instructions:
-     - '%eax = MOV32rm %rdi, 1, _, 0, _'
-     - 'CMP32ri8 %eax, 10, implicit-def %eflags'
-     # CHECK: [[@LINE+1]]:14: expected 32-bit integer (too large)
-     - 'JG_1 %bb.123456789123456, implicit %eflags'
- - id: 1
-   instructions:
-     - '%eax = MOV32r0 implicit-def %eflags'
- - id: 2
-   instructions:
-     - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    %eax = MOV32rm %rdi, 1, _, 0, _
+    CMP32ri8 %eax, 10, implicit-def %eflags
+    ; CHECK: [[@LINE+1]]:10: expected 32-bit integer (too large)
+    JG_1 %bb.123456789123456, implicit %eflags
+
+  bb.1:
+    %eax = MOV32r0 implicit-def %eflags
+
+  bb.2:
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir

@@ -14,13 +14,11 @@
 ...
 ---
 name: inc
-body:
-  - id: 0
-    name: entry
-    instructions:
-      # CHECK: [[@LINE+1]]:42: expected 64-bit integer (too large)
-      - '%rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _'
-      - '%eax = MOV32rm %rax, 1, _, 0, _'
-      - '%eax = INC32r %eax implicit-def %eflags'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    ; CHECK: [[@LINE+1]]:37: expected 64-bit integer (too large)
+    %rax = MOV64rm %rip, 1, _, @G + 123456789123456789123456789, _
+    %eax = MOV32rm %rax, 1, _, 0, _
+    %eax = INC32r %eax implicit-def %eflags
+    RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir

@@ -14,13 +14,11 @@ name:            test
 tracksRegLiveness: true
 liveins:
   - { reg: '%rdi' }
-body:
-  - id:          0
-    name:        entry
-    liveins:     [ '%rdi' ]
-    instructions:
-# CHECK: [[@LINE+1]]:58: expected 64-bit integer (too large)
-      - '%eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)'
-      - 'RETQ %eax'
+body: |
+  bb.0.entry:
+    liveins: %rdi
+  ; CHECK: [[@LINE+1]]:53: expected 64-bit integer (too large)
+    %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 12345678912345678924218574857 from %ir.a)
+    RETQ %eax
 ...