forked from OSchip/llvm-project
[X86] Pull out combineOrShiftToFunnelShift helper. NFCI.
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@ -39587,61 +39587,13 @@ static SDValue combineOrCmpEqZeroToCtlzSrl(SDNode *N, SelectionDAG &DAG,
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return Ret;
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return Ret;
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}
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}
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static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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static SDValue combineOrShiftToFunnelShift(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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const X86Subtarget &Subtarget) {
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assert(N->getOpcode() == ISD::OR && "Expected ISD::OR node");
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SDValue N0 = N->getOperand(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue N1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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// If this is SSE1 only convert to FOR to avoid scalarization.
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if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) {
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return DAG.getBitcast(MVT::v4i32,
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DAG.getNode(X86ISD::FOR, SDLoc(N), MVT::v4f32,
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DAG.getBitcast(MVT::v4f32, N0),
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DAG.getBitcast(MVT::v4f32, N1)));
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}
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// Match any-of bool scalar reductions into a bitcast/movmsk + cmp.
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// TODO: Support multiple SrcOps.
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if (VT == MVT::i1) {
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SmallVector<SDValue, 2> SrcOps;
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if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps) &&
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SrcOps.size() == 1) {
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SDLoc dl(N);
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unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
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EVT MaskVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
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SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget);
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if (Mask) {
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APInt AllBits = APInt::getNullValue(NumElts);
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return DAG.getSetCC(dl, MVT::i1, Mask,
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DAG.getConstant(AllBits, dl, MaskVT), ISD::SETNE);
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}
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}
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}
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
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return FPLogic;
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if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
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return R;
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if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
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return R;
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// Attempt to recursively combine an OR of shuffles.
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if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
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return Res;
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}
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if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
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if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
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return SDValue();
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return SDValue();
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@ -39764,6 +39716,67 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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return SDValue();
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}
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}
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static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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EVT VT = N->getValueType(0);
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// If this is SSE1 only convert to FOR to avoid scalarization.
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if (Subtarget.hasSSE1() && !Subtarget.hasSSE2() && VT == MVT::v4i32) {
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return DAG.getBitcast(MVT::v4i32,
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DAG.getNode(X86ISD::FOR, SDLoc(N), MVT::v4f32,
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DAG.getBitcast(MVT::v4f32, N0),
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DAG.getBitcast(MVT::v4f32, N1)));
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}
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// Match any-of bool scalar reductions into a bitcast/movmsk + cmp.
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// TODO: Support multiple SrcOps.
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if (VT == MVT::i1) {
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SmallVector<SDValue, 2> SrcOps;
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if (matchScalarReduction(SDValue(N, 0), ISD::OR, SrcOps) &&
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SrcOps.size() == 1) {
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SDLoc dl(N);
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unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements();
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EVT MaskVT = EVT::getIntegerVT(*DAG.getContext(), NumElts);
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SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget);
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if (Mask) {
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APInt AllBits = APInt::getNullValue(NumElts);
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return DAG.getSetCC(dl, MVT::i1, Mask,
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DAG.getConstant(AllBits, dl, MaskVT), ISD::SETNE);
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}
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}
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}
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if (DCI.isBeforeLegalizeOps())
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return SDValue();
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if (SDValue R = combineCompareEqual(N, DAG, DCI, Subtarget))
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return R;
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if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
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return FPLogic;
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if (SDValue R = canonicalizeBitSelect(N, DAG, Subtarget))
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return R;
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if (SDValue R = combineLogicBlendIntoPBLENDV(N, DAG, Subtarget))
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return R;
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if (SDValue R = combineOrShiftToFunnelShift(N, DAG, Subtarget))
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return R;
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// Attempt to recursively combine an OR of shuffles.
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if (VT.isVector() && (VT.getScalarSizeInBits() % 8) == 0) {
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(Op, DAG, Subtarget))
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return Res;
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}
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return SDValue();
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}
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/// Try to turn tests against the signbit in the form of:
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/// Try to turn tests against the signbit in the form of:
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/// XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
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/// XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
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/// into:
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/// into:
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