[Hexagon] MC testcases for verifying packetization rules

llvm/test/MC/Hexagon/PacketRules/bundle_option.s

@@ -0,0 +1,4 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+
+{ nop }:junk
+# CHECK: 3:9: error: 'junk' is not a valid bundle option

llvm/test/MC/Hexagon/PacketRules/cof_max1.s

@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -triple=hexagon -filetype=asm %s 2>&1 | FileCheck %s
+
+{ jumpr r0
+  jumpr r0 }
+# CHECK: 3:3: error: Instruction may not be in a packet with other branches
+
+{ jump unknown
+  if (p0) jump unknown }
+# CHECK: 7:3: error: Instruction may not be the first branch in packet
+

llvm/test/MC/Hexagon/PacketRules/newvalue_producers.s

@@ -0,0 +1,46 @@
+# RUN: not llvm-mc -arch=hexagon -mhvx -filetype=asm %s 2>%t; FileCheck %s <%t
+
+{ r0=memw(r1=##0)
+  memw(r0)=r1.new }
+# CHECK: 3:3: note: Absolute-set registers cannot be a new-value producer
+# CHECK: 4:3: error: Instruction does not have a valid new register producer
+
+{ r1:0=r1:0
+  memw(r0)=r0.new }
+# CHECK: 8:3: note: Double registers cannot be new-value producers
+# CHECK: 9:3: error: Instruction does not have a valid new register producer
+
+{ r1=memw(r0++m0)
+  memw(r0)=r0.new }
+# CHECK: 13:3: note: Auto-increment registers cannot be a new-value producer
+# CHECK: 14:3: error: Instruction does not have a valid new register producer
+
+{ r0=sfadd(r0,r0)
+  if (cmp.eq(r0.new,r0)) jump:t 0x0 }
+# CHECK: 18:3: note: FPU instructions cannot be new-value producers for jumps
+# CHECK: 19:3: error: Instruction does not have a valid new register producer
+
+{ v0=vmem(r0++m0)
+  memw(r0)=r0.new }
+# CHECK: 23:3: note: Auto-increment registers cannot be a new-value producer
+# CHECK: 24:3: error: Instruction does not have a valid new register producer
+
+{ if (p0) r0=r0
+  if (!p0) memw(r0)=r0.new }
+# CHECK: 28:3: note: Register producer has the opposite predicate sense as consumer
+# CHECK: 29:3: error: Instruction does not have a valid new register producer
+
+{ if (p0) r0=r0
+  memw(r0)=r0.new }
+# CHECK: 33:3: note: Register producer is predicated and consumer is unconditional
+# CHECK: 34:3: error: Instruction does not have a valid new register producer
+
+{ if (p0) r0=r0
+  if (cmp.eq(r0.new,r0)) jump:t 0x0 }
+# CHECK: 38:3: note: Register producer is predicated and consumer is unconditional
+# CHECK: 39:3: error: Instruction does not have a valid new register producer
+
+{ r0=memw(r1=##0)
+  if (p0) memw(r0)=r1.new }
+# CHECK: 43:3: note: Absolute-set registers cannot be a new-value producer
+# CHECK: 44:3: error: Instruction does not have a valid new register producer

llvm/test/MC/Hexagon/PacketRules/newvalue_producers_pass.s

@@ -0,0 +1,41 @@
+# RUN: llvm-mc -arch=hexagon -mhvx -mcpu=hexagonv65 -filetype=obj %s | llvm-objdump --mattr=+hvxv65 -d - | FileCheck %s
+
+{ r0=r0
+  memw(r0)=r0.new }
+# CHECK: { r0 = r0
+# CHECK:   memw(r0+#0) = r0.new }
+
+{ v0=v0
+  vmem(r0)=v0.new }
+# CHECK: { v0 = v0
+# CHECK:   vmem(r0+#0) = v0.new }
+
+{ v1:0=v1:0
+  vmem(r0)=v0.new }
+# CHECK: { v1:0 = vcombine(v1,v0)
+# CHECK:   vmem(r0+#0) = v0.new }
+
+{ r0=r0
+  if (cmp.eq(r0.new,r0)) jump:t 0x0 }
+# CHECK: { r0 = r0
+# CHECK:   if (cmp.eq(r0.new,r0)) jump:t 0x18
+
+{ vtmp.h=vgather(r0,m0,v0.h).h
+  vmem(r0)=vtmp.new }
+# CHECK: { vtmp.h = vgather(r0,m0,v0.h).h
+# CHECK:   vmem(r0+#0) = vtmp.new }
+
+{ if (p0) r0=r0
+  if (p0) memw(r0)=r0.new }
+# CHECK: { if (p0) r0 = add(r0,#0)
+# CHECK:   if (p0) memw(r0+#0) = r0.new }
+
+{ r0=r0
+  if (p0) memw(r0)=r0.new }
+# CHECK: { r0 = r0
+# CHECK:   if (p0) memw(r0+#0) = r0.new }
+
+{ r0=r0
+  if (!p0) memw(r0)=r0.new }
+# CHECK: { r0 = r0
+# CHECK:   if (!p0) memw(r0+#0) = r0.new }

llvm/test/MC/Hexagon/PacketRules/restrict_ax.s

@@ -1,4 +1,5 @@
+# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s <%t
+
 { r0=memw_locked(r0)
-  r1=-mpyi(r0,#0) }
-# RUN: not llvm-mc -arch=hexagon -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK00 <%t
-# CHECK00: 1:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions
+  r1=sfadd(r0,r0) }
+# CHECK: 3:3: error: Instruction can only be in a packet with ALU or non-FPU XTYPE instructions

llvm/test/MC/Hexagon/PacketRules/restrict_no_slot1_store_pass.s

@@ -0,0 +1,11 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+{ r0=sub(#1,r0)
+  r1=sub(#1, r0)
+  r2=sub(#1, r0)
+  if (p3) dealloc_return }
+
+# CHECK: { r0 = sub(#1,r0)
+# CHECK:   r1 = sub(#1,r0)
+# CHECK:   r2 = sub(#1,r0)
+# CHECK:   if (p3) dealloc_return }

llvm/test/MC/Hexagon/PacketRules/restrict_slot1_aok_pass.s

@@ -0,0 +1,11 @@
+# RUN: llvm-mc -arch=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+{ r0=sub(#1,r0)
+  r1=sub(#1, r0)
+  r2=sub(#1, r0)
+  dczeroa(r0) }
+
+# CHECK: { r0 = sub(#1,r0)
+# CHECK:   r1 = sub(#1,r0)
+# CHECK:   r2 = sub(#1,r0)
+# CHECK:   dczeroa(r0) }