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Handle regmask operands in ARMInstrInfo. 

llvm-svn: 150833
This commit is contained in:
Jakob Stoklund Olesen 2012-02-17 19:23:15 +00:00
parent 86f94ce509
commit 4fad5b2b9e
2 changed files with 9 additions and 7 deletions
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14
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -503,15 +503,11 @@ SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const { std::vector<MachineOperand> &Pred) const {
// FIXME: This confuses implicit_def with optional CPSR def.
const MCInstrDesc &MCID = MI->getDesc();
if (!MCID.getImplicitDefs() && !MI->hasOptionalDef())
return false;
bool Found = false; bool Found = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
(MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
Pred.push_back(MO); Pred.push_back(MO);
Found = true; Found = true;
} }
@ -1797,6 +1793,8 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) { for (unsigned IO = 0, EO = Instr.getNumOperands(); IO != EO; ++IO) {
const MachineOperand &MO = Instr.getOperand(IO); const MachineOperand &MO = Instr.getOperand(IO);
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR))
return false;
if (!MO.isReg()) continue; if (!MO.isReg()) continue;
// This instruction modifies or uses CPSR after the one we want to // This instruction modifies or uses CPSR after the one we want to
@ -1858,6 +1856,10 @@ OptimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, int CmpMask,
for (unsigned IO = 0, EO = Instr.getNumOperands(); for (unsigned IO = 0, EO = Instr.getNumOperands();
!isSafe && IO != EO; ++IO) { !isSafe && IO != EO; ++IO) {
const MachineOperand &MO = Instr.getOperand(IO); const MachineOperand &MO = Instr.getOperand(IO);
if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
isSafe = true;
break;
}
if (!MO.isReg() || MO.getReg() != ARM::CPSR) if (!MO.isReg() || MO.getReg() != ARM::CPSR)
continue; continue;
if (MO.isDef()) { if (MO.isDef()) {

2
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -586,7 +586,7 @@ Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
if (!(NCC == CC || NCC == OCC) || if (!(NCC == CC || NCC == OCC) ||
NMI->modifiesRegister(SrcReg, &TRI) || NMI->modifiesRegister(SrcReg, &TRI) ||
NMI->definesRegister(ARM::CPSR)) NMI->modifiesRegister(ARM::CPSR, &TRI))
break; break;
if (++NumInsts == 4) if (++NumInsts == 4)
// Too many in a row! // Too many in a row!