forked from OSchip/llvm-project
[x86] make tests immune to scalarization improvements; NFC
llvm-svn: 349176
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298e268155
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@ -881,12 +881,12 @@ define <4 x float> @stack_fold_extractf128(<8 x float> %a0, <8 x float> %a1) {
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ret <4 x float> %1
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}
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define i32 @stack_fold_extractps(<4 x float> %a0) {
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define i32 @stack_fold_extractps(<4 x float> %a0, <4 x float> %a1) {
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;CHECK-LABEL: stack_fold_extractps
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;CHECK: vextractps $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
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;CHECK: movl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
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; fadd forces execution domain
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%1 = fadd <4 x float> %a0, <float 1.0, float 2.0, float 3.0, float 4.0>
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%1 = fadd <4 x float> %a0, %a1
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%2 = extractelement <4 x float> %1, i32 1
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%3 = bitcast float %2 to i32
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%4 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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@ -624,12 +624,12 @@ define <4 x float> @stack_fold_dpps(<4 x float> %a0, <4 x float> %a1) {
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}
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declare <4 x float> @llvm.x86.sse41.dpps(<4 x float>, <4 x float>, i8) nounwind readnone
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define i32 @stack_fold_extractps(<4 x float> %a0) {
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define i32 @stack_fold_extractps(<4 x float> %a0, <4 x float> %a1) {
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;CHECK-LABEL: stack_fold_extractps
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;CHECK: extractps $1, {{%xmm[0-9][0-9]*}}, {{-?[0-9]*}}(%rsp) {{.*#+}} 4-byte Folded Spill
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;CHECK: movl {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Reload
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; fadd forces execution domain
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%1 = fadd <4 x float> %a0, <float 1.0, float 2.0, float 3.0, float 4.0>
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%1 = fadd <4 x float> %a0, %a1
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%2 = extractelement <4 x float> %1, i32 1
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%3 = bitcast float %2 to i32
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%4 = tail call <2 x i64> asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
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