forked from OSchip/llvm-project
[RISCV] Fix use of side-effects in asserts in decoder functions
llvm-svn: 369580
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359840a6e4
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@ -303,8 +303,9 @@ static DecodeStatus decodeRVCInstrSImm(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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(void)SImm6;
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return MCDisassembler::Success;
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}
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@ -315,8 +316,9 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, unsigned Insn,
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DecodeGPRRegisterClass(Inst, 0, Address, Decoder);
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uint64_t SImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeSImmOperand<6>(Inst, SImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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(void)SImm6;
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return MCDisassembler::Success;
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}
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@ -328,8 +330,9 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, unsigned Insn,
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Inst.addOperand(Inst.getOperand(0));
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uint64_t UImm6 =
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fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5);
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assert(decodeUImmOperand<6>(Inst, UImm6, Address, Decoder) ==
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MCDisassembler::Success && "Invalid immediate");
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DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder);
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(void)Result;
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assert(Result == MCDisassembler::Success && "Invalid immediate");
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(void)UImm6;
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return MCDisassembler::Success;
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}
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