forked from OSchip/llvm-project
[x86] add test/run for mayLoadFold with alignment; NFC
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622150ad5f
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4f423e9127
llvm/test/CodeGen/X86
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@ -1,6 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3 | FileCheck %s --check-prefixes=X64,ALIGN
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2,+ssse3,sse-unaligned-mem | FileCheck %s --check-prefixes=X64,UNALIGN
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; There are no MMX operations in @t1
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@ -92,6 +93,38 @@ define <4 x float> @t4(<4 x float>* %P) nounwind {
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ret <4 x float> %tmp2
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}
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define <4 x float> @t4_under_aligned(<4 x float>* %P) nounwind {
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; X32-LABEL: t4_under_aligned:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movups (%eax), %xmm1
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; X32-NEXT: xorps %xmm2, %xmm2
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; X32-NEXT: xorps %xmm0, %xmm0
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[3,0]
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
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; X32-NEXT: retl
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;
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; ALIGN-LABEL: t4_under_aligned:
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; ALIGN: # %bb.0:
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; ALIGN-NEXT: movups (%rdi), %xmm1
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; ALIGN-NEXT: xorps %xmm2, %xmm2
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; ALIGN-NEXT: xorps %xmm0, %xmm0
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; ALIGN-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[3,0]
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; ALIGN-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[2,3]
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; ALIGN-NEXT: retq
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;
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; UNALIGN-LABEL: t4_under_aligned:
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; UNALIGN: # %bb.0:
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; UNALIGN-NEXT: xorps %xmm1, %xmm1
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; UNALIGN-NEXT: xorps %xmm0, %xmm0
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; UNALIGN-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],mem[3,0]
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; UNALIGN-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
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; UNALIGN-NEXT: retq
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%tmp1 = load <4 x float>, <4 x float>* %P, align 4
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%tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
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ret <4 x float> %tmp2
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}
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define <16 x i8> @t5(<16 x i8> %x) nounwind {
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; X32-LABEL: t5:
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; X32: # %bb.0:
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