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Fix alignment of arm64 fpu register context structure 

so it has the same padding as the kernel's definition
which is written in terms of uint128_t.  Original patch
by Ryan Mansfield.

<rdar://problem/35468499> 

llvm-svn: 318357
This commit is contained in:
Jason Molenda 2017-11-16 00:50:29 +00:00
parent f76f315436
commit 4f34614beb
3 changed files with 4 additions and 4 deletions
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2
lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
View File

@ -686,7 +686,7 @@ public:
case FPURegSet: {
uint8_t *fpu_reg_buf = (uint8_t *)&fpu.v[0];
const int fpu_reg_buf_size = sizeof(fpu);
if (fpu_reg_buf_size == count &&
if (fpu_reg_buf_size == count * sizeof(uint32_t) &&
data.ExtractBytes(offset, fpu_reg_buf_size, eByteOrderLittle,
fpu_reg_buf) == fpu_reg_buf_size) {
SetError(FPURegSet, Read, 0);

4
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
View File

@ -426,7 +426,7 @@ bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
case fpu_v29:
case fpu_v30:
case fpu_v31:
value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size,
value.SetBytes(fpu.v[reg].bytes.buffer, reg_info->byte_size,
endian::InlHostByteOrder());
break;
@ -618,7 +618,7 @@ bool RegisterContextDarwin_arm64::WriteRegister(const RegisterInfo *reg_info,
case fpu_v29:
case fpu_v30:
case fpu_v31:
::memcpy(fpu.v[reg].bytes, value.GetBytes(), value.GetByteSize());
::memcpy(fpu.v[reg].bytes.buffer, value.GetBytes(), value.GetByteSize());
break;
case fpu_fpsr:

2
lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.h
View File

@ -78,7 +78,7 @@ public:
};
struct VReg {
uint8_t bytes[16];
llvm::AlignedCharArray<16, 16> bytes;
};
// mirrors <mach/arm/thread_status.h> arm_neon_state64_t