forked from OSchip/llvm-project
[AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16
See bugs 36092, 36093:
https://bugs.llvm.org/show_bug.cgi?id=36092
https://bugs.llvm.org/show_bug.cgi?id=36093
Differential Revision: https://reviews.llvm.org/D42583
Reviewers: vpykhtin, artem.tamazov, arsenm
llvm-svn: 323651
This commit is contained in:
Dmitry Preobrazhensky
parent
bda7568dd8
commit
4f321aef74
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@ -138,6 +138,7 @@ public:
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ImmTyGLC,
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ImmTySLC,
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ImmTyTFE,
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ImmTyD16,
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ImmTyClampSI,
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ImmTyOModSI,
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ImmTyDppCtrl,
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@ -286,7 +287,7 @@ public:
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bool isDMask() const { return isImmTy(ImmTyDMask); }
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bool isUNorm() const { return isImmTy(ImmTyUNorm); }
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bool isDA() const { return isImmTy(ImmTyDA); }
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bool isR128() const { return isImmTy(ImmTyUNorm); }
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bool isR128() const { return isImmTy(ImmTyR128); }
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bool isLWE() const { return isImmTy(ImmTyLWE); }
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bool isOff() const { return isImmTy(ImmTyOff); }
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bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
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@ -305,6 +306,7 @@ public:
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bool isGLC() const { return isImmTy(ImmTyGLC); }
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bool isSLC() const { return isImmTy(ImmTySLC); }
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bool isTFE() const { return isImmTy(ImmTyTFE); }
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bool isD16() const { return isImmTy(ImmTyD16); }
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bool isDFMT() const { return isImmTy(ImmTyDFMT) && isUInt<8>(getImm()); }
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bool isNFMT() const { return isImmTy(ImmTyNFMT) && isUInt<8>(getImm()); }
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bool isBankMask() const { return isImmTy(ImmTyDppBankMask); }
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@ -657,6 +659,7 @@ public:
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case ImmTyGLC: OS << "GLC"; break;
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case ImmTySLC: OS << "SLC"; break;
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case ImmTyTFE: OS << "TFE"; break;
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case ImmTyD16: OS << "D16"; break;
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case ImmTyDFMT: OS << "DFMT"; break;
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case ImmTyNFMT: OS << "NFMT"; break;
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case ImmTyClampSI: OS << "ClampSI"; break;
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@ -821,7 +824,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
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// Number of extra operands parsed after the first optional operand.
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// This may be necessary to skip hardcoded mandatory operands.
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static const unsigned MAX_OPR_LOOKAHEAD = 1;
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static const unsigned MAX_OPR_LOOKAHEAD = 8;
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unsigned ForcedEncodingSize = 0;
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bool ForcedDPP = false;
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@ -1081,6 +1084,7 @@ public:
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AMDGPUOperand::Ptr defaultSLC() const;
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AMDGPUOperand::Ptr defaultTFE() const;
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AMDGPUOperand::Ptr defaultD16() const;
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AMDGPUOperand::Ptr defaultDMask() const;
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AMDGPUOperand::Ptr defaultUNorm() const;
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AMDGPUOperand::Ptr defaultDA() const;
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@ -4016,6 +4020,10 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultTFE() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyTFE);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultD16() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyD16);
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}
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void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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const OperandVector &Operands,
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bool IsAtomic, bool IsAtomicReturn) {
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@ -4260,6 +4268,7 @@ static const OptionalOperand AMDGPUOptionalOperandTable[] = {
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{"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
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{"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
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{"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
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{"d16", AMDGPUOperand::ImmTyD16, true, nullptr},
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{"high", AMDGPUOperand::ImmTyHigh, true, nullptr},
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{"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
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{"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
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@ -4964,6 +4973,8 @@ unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
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return Operand.isGDS() ? Match_Success : Match_InvalidOperand;
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case MCK_glc:
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return Operand.isGLC() ? Match_Success : Match_InvalidOperand;
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case MCK_d16:
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return Operand.isD16() ? Match_Success : Match_InvalidOperand;
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case MCK_idxen:
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return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;
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case MCK_offen:
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@ -836,6 +836,7 @@ def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
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def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
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def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
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def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
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def D16 : NamedOperandBit<"D16", NamedMatchClass<"D16">>;
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def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
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def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
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@ -18,6 +18,16 @@ image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe
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// SICI: image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
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// VI: image_load v[4:7], v[237:240], s[28:35] dmask:0x7 tfe ; encoding: [0x00,0x07,0x01,0xf0,0xed,0x04,0x07,0x00]
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// Verify support of all possible modifiers.
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// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
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// FIXME: Check that d16 is not supported before VI
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image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16
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// VI: image_load v[5:6], v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
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// FIXME: Check that d16 is not supported before VI
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image_load v5, v[1:4], s[8:15] d16
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// VI: image_load v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x00,0xf0,0x01,0x05,0x02,0x80]
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image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
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// SICI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
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// VI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
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@ -30,6 +40,16 @@ image_store v[193:194], v[237:240], s[28:35] tfe
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// SICI: image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
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// VI: image_store v[193:194], v[237:240], s[28:35] tfe ; encoding: [0x00,0x00,0x21,0xf0,0xed,0xc1,0x07,0x00]
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// Verify support of all possible modifiers.
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// FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
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// FIXME: Check that d16 is not supported before VI
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image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16
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// VI: image_store v5, v[1:4], s[8:15] dmask:0x1 unorm glc slc r128 lwe da d16 ; encoding: [0x00,0xf1,0x22,0xf2,0x01,0x05,0x02,0x80]
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// FIXME: Check that d16 is not supported before VI
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image_store v5, v[1:4], s[8:15] d16
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// VI: image_store v5, v[1:4], s[8:15] d16 ; encoding: [0x00,0x00,0x20,0xf0,0x01,0x05,0x02,0x80]
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//===----------------------------------------------------------------------===//
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// Image Sample
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//===----------------------------------------------------------------------===//
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@ -28,6 +28,12 @@
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# VI: image_store v0, v1, s[0:7] dmask:0x1 unorm ; encoding: [0x00,0x11,0x20,0xf0,0x01,0x00,0x00,0x00]
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0x00 0x11 0x20 0xf0 0x01 0x00 0x00 0x00
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# Test all modifiers
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# FIXME: This test is incorrect because r128 assumes a 128-bit SRSRC.
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# FIXME: This test is incorrect because tfe shall increase data size by 1.
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# VI: image_load v5, v1, s[8:15] dmask:0x1 unorm glc slc r128 tfe lwe da d16 ; encoding: [0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80]
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0x00,0xf1,0x03,0xf2,0x01,0x05,0x02,0x80
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# Test dmask == 0
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# VI: image_load v0, v4, s[8:15] unorm ; encoding: [0x00,0x10,0x00,0xf0,0x04,0x00,0x02,0x00]
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0x00 0x10 0x00 0xf0 0x04 0x00 0x02 0x00
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