forked from OSchip/llvm-project
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
llvm-svn: 138795
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@ -96,3 +96,6 @@
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# CHECK: vcvtsd2si %xmm0, %rax
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0xc4 0xe1 0xfb 0x2d 0xc0
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# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax)
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0xc4 0xe2 0x71 0x2f 0x00
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@ -623,20 +623,43 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
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case X86Local::MRMDestReg:
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// Operand 1 is a register operand in the R/M field.
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// Operand 2 is a register operand in the Reg/Opcode field.
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// - In AVX, there is a register operand in the VEX.vvvv field here -
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// Operand 3 (optional) is an immediate.
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if (HasVEX_4VPrefix)
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assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
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"Unexpected number of operands for MRMDestRegFrm with VEX_4V");
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else
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assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
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"Unexpected number of operands for MRMDestRegFrm");
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HANDLE_OPERAND(rmRegister)
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if (HasVEX_4VPrefix)
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// FIXME: In AVX, the register below becomes the one encoded
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// in ModRMVEX and the one above the one in the VEX.VVVV field
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HANDLE_OPERAND(vvvvRegister)
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HANDLE_OPERAND(roRegister)
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HANDLE_OPTIONAL(immediate)
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break;
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case X86Local::MRMDestMem:
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// Operand 1 is a memory operand (possibly SIB-extended)
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// Operand 2 is a register operand in the Reg/Opcode field.
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// - In AVX, there is a register operand in the VEX.vvvv field here -
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// Operand 3 (optional) is an immediate.
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if (HasVEX_4VPrefix)
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assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
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"Unexpected number of operands for MRMDestMemFrm with VEX_4V");
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else
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assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
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"Unexpected number of operands for MRMDestMemFrm");
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HANDLE_OPERAND(memory)
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if (HasVEX_4VPrefix)
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// FIXME: In AVX, the register below becomes the one encoded
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// in ModRMVEX and the one above the one in the VEX.VVVV field
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HANDLE_OPERAND(vvvvRegister)
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HANDLE_OPERAND(roRegister)
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HANDLE_OPTIONAL(immediate)
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break;
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