forked from OSchip/llvm-project
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix. cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix. Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein. llvm-svn: 171668
This commit is contained in:
Craig Topper
parent
5f3c9200e5
commit
4f1c7256f9
|
|
@ -1435,7 +1435,7 @@ defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
|
|||
SSE_CVT_SS2SI_32>,
|
||||
XS, VEX, VEX_LIG;
|
||||
defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
|
||||
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
"cvttss2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SS2SI_64>,
|
||||
XS, VEX, VEX_W, VEX_LIG;
|
||||
defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
|
||||
|
|
@ -1443,26 +1443,43 @@ defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
|
|||
SSE_CVT_SD2SI>,
|
||||
XD, VEX, VEX_LIG;
|
||||
defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
|
||||
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SD2SI>,
|
||||
XD, VEX, VEX_W, VEX_LIG;
|
||||
|
||||
def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
|
||||
def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
|
||||
def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
|
||||
def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
|
||||
def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
|
||||
def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
|
||||
def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
|
||||
def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
|
||||
|
||||
// The assembler can recognize rr 64-bit instructions by seeing a rxx
|
||||
// register, but the same isn't true when only using memory operands,
|
||||
// provide other assembly "l" and "q" forms to address this explicitly
|
||||
// where appropriate to do so.
|
||||
defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
|
||||
defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
|
||||
XS, VEX_4V, VEX_LIG;
|
||||
defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
|
||||
XS, VEX_4V, VEX_W, VEX_LIG;
|
||||
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
|
||||
defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
|
||||
XD, VEX_4V, VEX_LIG;
|
||||
defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
|
||||
XD, VEX_4V, VEX_W, VEX_LIG;
|
||||
|
||||
def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
|
||||
(VCVTSI2SDrr FR64:$dst, FR64:$src1, GR32:$src)>;
|
||||
def : InstAlias<"vcvtsi2sd{l}\t{$src, $src1, $dst|$dst, $src1, $src}",
|
||||
def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
|
||||
(VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
|
||||
def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
|
||||
(VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
|
||||
|
||||
let Predicates = [HasAVX] in {
|
||||
|
|
@ -1489,27 +1506,49 @@ defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
|
|||
"cvttss2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SS2SI_32>, XS;
|
||||
defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
|
||||
"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
"cvttss2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SS2SI_64>, XS, REX_W;
|
||||
defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
|
||||
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SD2SI>, XD;
|
||||
defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
|
||||
"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
"cvttsd2si\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_SD2SI>, XD, REX_W;
|
||||
defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
|
||||
"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
||||
"cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_Scalar>, XS;
|
||||
defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
|
||||
"cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_Scalar>, XS, REX_W;
|
||||
defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
|
||||
"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
||||
"cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_Scalar>, XD;
|
||||
defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
|
||||
"cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
|
||||
SSE_CVT_Scalar>, XD, REX_W;
|
||||
|
||||
def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
|
||||
def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
|
||||
def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
|
||||
def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
|
||||
def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
|
||||
def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
|
||||
def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
|
||||
def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
|
||||
|
||||
def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
|
||||
(CVTSI2SSrm FR64:$dst, i32mem:$src)>;
|
||||
def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
|
||||
(CVTSI2SDrm FR64:$dst, i32mem:$src)>;
|
||||
|
||||
// Conversion Instructions Intrinsics - Match intrinsics which expect MM
|
||||
// and/or XMM operand(s).
|
||||
|
||||
|
|
@ -1544,27 +1583,27 @@ multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
|
|||
}
|
||||
|
||||
defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
|
||||
int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si{l}",
|
||||
int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
|
||||
SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
|
||||
defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
|
||||
int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si{q}",
|
||||
int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
|
||||
SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
|
||||
|
||||
defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
|
||||
sdmem, sse_load_f64, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
|
||||
sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
|
||||
defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
|
||||
sdmem, sse_load_f64, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
|
||||
sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
|
||||
|
||||
|
||||
defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
|
||||
int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
|
||||
int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
|
||||
SSE_CVT_Scalar, 0>, XS, VEX_4V;
|
||||
defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
|
||||
int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
|
||||
SSE_CVT_Scalar, 0>, XS, VEX_4V,
|
||||
VEX_W;
|
||||
defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
|
||||
int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
|
||||
int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
|
||||
SSE_CVT_Scalar, 0>, XD, VEX_4V;
|
||||
defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
|
||||
int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
|
||||
|
|
@ -1574,13 +1613,13 @@ defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
|
|||
let Constraints = "$src1 = $dst" in {
|
||||
defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
|
||||
int_x86_sse_cvtsi2ss, i32mem, loadi32,
|
||||
"cvtsi2ss", SSE_CVT_Scalar>, XS;
|
||||
"cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
|
||||
defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
|
||||
int_x86_sse_cvtsi642ss, i64mem, loadi64,
|
||||
"cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
|
||||
defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
|
||||
int_x86_sse2_cvtsi2sd, i32mem, loadi32,
|
||||
"cvtsi2sd", SSE_CVT_Scalar>, XD;
|
||||
"cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
|
||||
defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
|
||||
int_x86_sse2_cvtsi642sd, i64mem, loadi64,
|
||||
"cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
|
||||
|
|
@ -1594,40 +1633,40 @@ defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
|
|||
SSE_CVT_SS2SI_32>, XS, VEX;
|
||||
defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
|
||||
int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
|
||||
"cvttss2si{q}", SSE_CVT_SS2SI_64>,
|
||||
"cvttss2si", SSE_CVT_SS2SI_64>,
|
||||
XS, VEX, VEX_W;
|
||||
defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
|
||||
sdmem, sse_load_f64, "cvttsd2si",
|
||||
SSE_CVT_SD2SI>, XD, VEX;
|
||||
defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
|
||||
int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
|
||||
"cvttsd2si{q}", SSE_CVT_SD2SI>,
|
||||
"cvttsd2si", SSE_CVT_SD2SI>,
|
||||
XD, VEX, VEX_W;
|
||||
defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
|
||||
ssmem, sse_load_f32, "cvttss2si",
|
||||
SSE_CVT_SS2SI_32>, XS;
|
||||
defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
|
||||
int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
|
||||
"cvttss2si{q}", SSE_CVT_SS2SI_64>, XS, REX_W;
|
||||
"cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
|
||||
defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
|
||||
sdmem, sse_load_f64, "cvttsd2si",
|
||||
SSE_CVT_SD2SI>, XD;
|
||||
defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
|
||||
int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
|
||||
"cvttsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
|
||||
"cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
|
||||
|
||||
defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
|
||||
ssmem, sse_load_f32, "cvtss2si{l}",
|
||||
ssmem, sse_load_f32, "cvtss2si",
|
||||
SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
|
||||
defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
|
||||
ssmem, sse_load_f32, "cvtss2si{q}",
|
||||
ssmem, sse_load_f32, "cvtss2si",
|
||||
SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
|
||||
|
||||
defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
|
||||
ssmem, sse_load_f32, "cvtss2si{l}",
|
||||
ssmem, sse_load_f32, "cvtss2si",
|
||||
SSE_CVT_SS2SI_32>, XS;
|
||||
defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
|
||||
ssmem, sse_load_f32, "cvtss2si{q}",
|
||||
ssmem, sse_load_f32, "cvtss2si",
|
||||
SSE_CVT_SS2SI_64>, XS, REX_W;
|
||||
|
||||
defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
|
||||
|
|
@ -1644,6 +1683,40 @@ defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
|
|||
SSEPackedSingle, SSE_CVT_PS>,
|
||||
TB, Requires<[UseSSE2]>;
|
||||
|
||||
def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
|
||||
def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
|
||||
def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
|
||||
def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
|
||||
|
||||
def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
|
||||
def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
|
||||
def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
|
||||
def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
|
||||
def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
|
||||
(CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
|
||||
|
||||
/// SSE 2 Only
|
||||
|
||||
// Convert scalar double to scalar single
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ entry:
|
|||
ret double %conv
|
||||
}
|
||||
|
||||
; CHECK: vcvtsi2sd (%
|
||||
; CHECK: vcvtsi2sdl (%
|
||||
define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp {
|
||||
entry:
|
||||
%tmp1 = load i32* %e, align 4
|
||||
|
|
@ -54,7 +54,7 @@ entry:
|
|||
ret double %conv
|
||||
}
|
||||
|
||||
; CHECK: vcvtsi2ss (%
|
||||
; CHECK: vcvtsi2ssl (%
|
||||
define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp {
|
||||
entry:
|
||||
%tmp1 = load i32* %e, align 4
|
||||
|
|
|
|||
|
|
@ -55,10 +55,10 @@ while.end:
|
|||
; instructions, they are still dependent on themselves.
|
||||
; CHECK: xorps [[XMM1:%xmm[0-9]+]]
|
||||
; CHECK: , [[XMM1]]
|
||||
; CHECK: cvtsi2ss %{{.*}}, [[XMM1]]
|
||||
; CHECK: cvtsi2ssl %{{.*}}, [[XMM1]]
|
||||
; CHECK: xorps [[XMM2:%xmm[0-9]+]]
|
||||
; CHECK: , [[XMM2]]
|
||||
; CHECK: cvtsi2ss %{{.*}}, [[XMM2]]
|
||||
; CHECK: cvtsi2ssl %{{.*}}, [[XMM2]]
|
||||
;
|
||||
define float @f2(i32 %m) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
; RUN: llc < %s -mcpu=nehalem | not grep rsp
|
||||
; RUN: llc < %s -mcpu=nehalem | grep cvttsd2siq
|
||||
; RUN: llc < %s -mcpu=nehalem | grep cvttsd2si
|
||||
|
||||
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
|
||||
target triple = "x86_64-apple-darwin8"
|
||||
|
|
|
|||
|
|
@ -120,13 +120,13 @@
|
|||
# CHECK: vandps (%rdx), %xmm1, %xmm7
|
||||
0xc5 0xf0 0x54 0x3a
|
||||
|
||||
# CHECK: vcvtss2sil %xmm0, %eax
|
||||
# CHECK: vcvtss2si %xmm0, %eax
|
||||
0xc5 0xfa 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc5 0xfb 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2siq %xmm0, %rax
|
||||
# CHECK: vcvtsd2si %xmm0, %rax
|
||||
0xc4 0xe1 0xfb 0x2d 0xc0
|
||||
|
||||
# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax)
|
||||
|
|
@ -437,10 +437,10 @@
|
|||
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
|
||||
0xc4 0xe3 0x7d 0x0b 0xc0 0x00
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc4 0xe1 0x7f 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2siq %xmm0, %rax
|
||||
# CHECK: vcvtsd2si %xmm0, %rax
|
||||
0xc4 0xe1 0xff 0x2d 0xc0
|
||||
|
||||
# CHECK: vucomisd %xmm1, %xmm0
|
||||
|
|
|
|||
|
|
@ -156,13 +156,13 @@
|
|||
# CHECK: vandps (%edx), %xmm1, %xmm7
|
||||
0xc5 0xf0 0x54 0x3a
|
||||
|
||||
# CHECK: vcvtss2sil %xmm0, %eax
|
||||
# CHECK: vcvtss2si %xmm0, %eax
|
||||
0xc5 0xfa 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc5 0xfb 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc4 0xe1 0x7b 0x2d 0xc0
|
||||
|
||||
# CHECK: vmaskmovpd %xmm0, %xmm1, (%eax)
|
||||
|
|
@ -460,10 +460,10 @@
|
|||
# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0
|
||||
0xc4 0xe3 0x7d 0x0b 0xc0 0x00
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc4 0xe1 0x7f 0x2d 0xc0
|
||||
|
||||
# CHECK: vcvtsd2sil %xmm0, %eax
|
||||
# CHECK: vcvtsd2si %xmm0, %eax
|
||||
0xc4 0xe1 0xff 0x2d 0xc0
|
||||
|
||||
# CHECK: vucomisd %xmm1, %xmm0
|
||||
|
|
|
|||
|
|
@ -655,14 +655,22 @@
|
|||
// CHECK: encoding: [0xc5,0xfa,0x2c,0x01]
|
||||
vcvttss2si (%ecx), %eax
|
||||
|
||||
// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2
|
||||
// CHECK: vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
|
||||
vcvtsi2ss (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2ss (%eax), %xmm1, %xmm2
|
||||
// CHECK: vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
|
||||
vcvtsi2ss (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
|
||||
vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf2,0x2a,0x10]
|
||||
vcvtsi2ssl (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvttsd2si %xmm1, %eax
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2c,0xc1]
|
||||
vcvttsd2si %xmm1, %eax
|
||||
|
|
@ -671,14 +679,22 @@
|
|||
// CHECK: encoding: [0xc5,0xfb,0x2c,0x01]
|
||||
vcvttsd2si (%ecx), %eax
|
||||
|
||||
// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2
|
||||
// CHECK: vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
|
||||
vcvtsi2sd (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2sd (%eax), %xmm1, %xmm2
|
||||
// CHECK: vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
|
||||
vcvtsi2sd (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
|
||||
vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf3,0x2a,0x10]
|
||||
vcvtsi2sdl (%eax), %xmm1, %xmm2
|
||||
|
||||
// CHECK: vmovaps (%eax), %xmm2
|
||||
// CHECK: encoding: [0xc5,0xf8,0x28,0x10]
|
||||
vmovaps (%eax), %xmm2
|
||||
|
|
@ -767,14 +783,22 @@
|
|||
// CHECK: encoding: [0xc5,0xe8,0x12,0xd9]
|
||||
vmovhlps %xmm1, %xmm2, %xmm3
|
||||
|
||||
// CHECK: vcvtss2sil %xmm1, %eax
|
||||
// CHECK: vcvtss2si %xmm1, %eax
|
||||
// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1]
|
||||
vcvtss2si %xmm1, %eax
|
||||
|
||||
// CHECK: vcvtss2sil (%eax), %ebx
|
||||
// CHECK: vcvtss2si (%eax), %ebx
|
||||
// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
|
||||
vcvtss2si (%eax), %ebx
|
||||
|
||||
// CHECK: vcvtss2si %xmm1, %eax
|
||||
// CHECK: encoding: [0xc5,0xfa,0x2d,0xc1]
|
||||
vcvtss2sil %xmm1, %eax
|
||||
|
||||
// CHECK: vcvtss2si (%eax), %ebx
|
||||
// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
|
||||
vcvtss2sil (%eax), %ebx
|
||||
|
||||
// CHECK: vcvtdq2ps %xmm5, %xmm6
|
||||
// CHECK: encoding: [0xc5,0xf8,0x5b,0xf5]
|
||||
vcvtdq2ps %xmm5, %xmm6
|
||||
|
|
@ -3103,19 +3127,35 @@
|
|||
// CHECK: encoding: [0xc5,0xf8,0x77]
|
||||
vzeroupper
|
||||
|
||||
// CHECK: vcvtsd2sil %xmm4, %ecx
|
||||
// CHECK: vcvtsd2si %xmm4, %ecx
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2d,0xcc]
|
||||
vcvtsd2sil %xmm4, %ecx
|
||||
|
||||
// CHECK: vcvtsd2sil (%ecx), %ecx
|
||||
// CHECK: vcvtsd2si (%ecx), %ecx
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2d,0x09]
|
||||
vcvtsd2sil (%ecx), %ecx
|
||||
|
||||
// CHECK: vcvtsi2sd (%ebp), %xmm0, %xmm7
|
||||
// CHECK: vcvtsd2si %xmm4, %ecx
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2d,0xcc]
|
||||
vcvtsd2si %xmm4, %ecx
|
||||
|
||||
// CHECK: vcvtsd2si (%ecx), %ecx
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2d,0x09]
|
||||
vcvtsd2si (%ecx), %ecx
|
||||
|
||||
// CHECK: vcvtsi2sdl (%ebp), %xmm0, %xmm7
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2a,0x7d,0x00]
|
||||
vcvtsi2sdl (%ebp), %xmm0, %xmm7
|
||||
|
||||
// CHECK: vcvtsi2sdl (%esp), %xmm0, %xmm7
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2a,0x3c,0x24]
|
||||
vcvtsi2sdl (%esp), %xmm0, %xmm7
|
||||
|
||||
// CHECK: vcvtsi2sdl (%ebp), %xmm0, %xmm7
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2a,0x7d,0x00]
|
||||
vcvtsi2sd (%ebp), %xmm0, %xmm7
|
||||
|
||||
// CHECK: vcvtsi2sd (%esp), %xmm0, %xmm7
|
||||
// CHECK: vcvtsi2sdl (%esp), %xmm0, %xmm7
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2a,0x3c,0x24]
|
||||
vcvtsi2sd (%esp), %xmm0, %xmm7
|
||||
|
||||
|
|
|
|||
|
|
@ -896,11 +896,11 @@
|
|||
// CHECK: cvtps2pi %xmm5, %mm3
|
||||
cvtps2pi %xmm5,%mm3
|
||||
|
||||
// CHECK: cvtsi2ss %ecx, %xmm5
|
||||
cvtsi2ss %ecx,%xmm5
|
||||
// CHECK: cvtsi2ssl %ecx, %xmm5
|
||||
cvtsi2ssl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2ss 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
// CHECK: cvtsi2ssl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2ssl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: cvttps2pi 3735928559(%ebx,%ecx,8), %mm3
|
||||
cvttps2pi 0xdeadbeef(%ebx,%ecx,8),%mm3
|
||||
|
|
@ -1157,11 +1157,11 @@
|
|||
// CHECK: cvtpi2pd %mm3, %xmm5
|
||||
cvtpi2pd %mm3,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd %ecx, %xmm5
|
||||
cvtsi2sd %ecx,%xmm5
|
||||
// CHECK: cvtsi2sdl %ecx, %xmm5
|
||||
cvtsi2sdl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2sd 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
// CHECK: cvtsi2sdl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2sdl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: divpd %xmm5, %xmm5
|
||||
divpd %xmm5,%xmm5
|
||||
|
|
@ -7152,29 +7152,29 @@
|
|||
// CHECK: encoding: [0x0f,0x2d,0xdd]
|
||||
cvtps2pi %xmm5,%mm3
|
||||
|
||||
// CHECK: cvtsi2ss %ecx, %xmm5
|
||||
// CHECK: cvtsi2ssl %ecx, %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0xe9]
|
||||
cvtsi2ss %ecx,%xmm5
|
||||
cvtsi2ssl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 3735928559(%ebx,%ecx,8), %xmm5
|
||||
// CHECK: cvtsi2ssl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0xac,0xcb,0xef,0xbe,0xad,0xde]
|
||||
cvtsi2ss 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
cvtsi2ssl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 69, %xmm5
|
||||
// CHECK: cvtsi2ssl 69, %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0x2d,0x45,0x00,0x00,0x00]
|
||||
cvtsi2ss 0x45,%xmm5
|
||||
cvtsi2ssl 0x45,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 32493, %xmm5
|
||||
// CHECK: cvtsi2ssl 32493, %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0x2d,0xed,0x7e,0x00,0x00]
|
||||
cvtsi2ss 0x7eed,%xmm5
|
||||
cvtsi2ssl 0x7eed,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 3133065982, %xmm5
|
||||
// CHECK: cvtsi2ssl 3133065982, %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0x2d,0xfe,0xca,0xbe,0xba]
|
||||
cvtsi2ss 0xbabecafe,%xmm5
|
||||
cvtsi2ssl 0xbabecafe,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 305419896, %xmm5
|
||||
// CHECK: cvtsi2ssl 305419896, %xmm5
|
||||
// CHECK: encoding: [0xf3,0x0f,0x2a,0x2d,0x78,0x56,0x34,0x12]
|
||||
cvtsi2ss 0x12345678,%xmm5
|
||||
cvtsi2ssl 0x12345678,%xmm5
|
||||
|
||||
// CHECK: cvttps2pi 3735928559(%ebx,%ecx,8), %mm3
|
||||
// CHECK: encoding: [0x0f,0x2c,0x9c,0xcb,0xef,0xbe,0xad,0xde]
|
||||
|
|
@ -8660,29 +8660,29 @@
|
|||
// CHECK: encoding: [0x66,0x0f,0x2a,0xeb]
|
||||
cvtpi2pd %mm3,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd %ecx, %xmm5
|
||||
// CHECK: cvtsi2sdl %ecx, %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0xe9]
|
||||
cvtsi2sd %ecx,%xmm5
|
||||
cvtsi2sdl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 3735928559(%ebx,%ecx,8), %xmm5
|
||||
// CHECK: cvtsi2sdl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0xac,0xcb,0xef,0xbe,0xad,0xde]
|
||||
cvtsi2sd 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
cvtsi2sdl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 69, %xmm5
|
||||
// CHECK: cvtsi2sdl 69, %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0x2d,0x45,0x00,0x00,0x00]
|
||||
cvtsi2sd 0x45,%xmm5
|
||||
cvtsi2sdl 0x45,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 32493, %xmm5
|
||||
// CHECK: cvtsi2sdl 32493, %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0x2d,0xed,0x7e,0x00,0x00]
|
||||
cvtsi2sd 0x7eed,%xmm5
|
||||
cvtsi2sdl 0x7eed,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 3133065982, %xmm5
|
||||
// CHECK: cvtsi2sdl 3133065982, %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0x2d,0xfe,0xca,0xbe,0xba]
|
||||
cvtsi2sd 0xbabecafe,%xmm5
|
||||
cvtsi2sdl 0xbabecafe,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 305419896, %xmm5
|
||||
// CHECK: cvtsi2sdl 305419896, %xmm5
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2a,0x2d,0x78,0x56,0x34,0x12]
|
||||
cvtsi2sd 0x12345678,%xmm5
|
||||
cvtsi2sdl 0x12345678,%xmm5
|
||||
|
||||
// CHECK: divpd 3735928559(%ebx,%ecx,8), %xmm5
|
||||
// CHECK: encoding: [0x66,0x0f,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
|
||||
|
|
@ -16208,23 +16208,23 @@
|
|||
// CHECK: cvtps2pi %xmm5, %mm3
|
||||
cvtps2pi %xmm5,%mm3
|
||||
|
||||
// CHECK: cvtsi2ss %ecx, %xmm5
|
||||
cvtsi2ss %ecx,%xmm5
|
||||
// CHECK: cvtsi2ssl %ecx, %xmm5
|
||||
cvtsi2ssl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2ss 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
// CHECK: cvtsi2ssl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2ssl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 69, %xmm5
|
||||
cvtsi2ss 0x45,%xmm5
|
||||
// CHECK: cvtsi2ssl 69, %xmm5
|
||||
cvtsi2ssl 0x45,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 32493, %xmm5
|
||||
cvtsi2ss 0x7eed,%xmm5
|
||||
// CHECK: cvtsi2ssl 32493, %xmm5
|
||||
cvtsi2ssl 0x7eed,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 3133065982, %xmm5
|
||||
cvtsi2ss 0xbabecafe,%xmm5
|
||||
// CHECK: cvtsi2ssl 3133065982, %xmm5
|
||||
cvtsi2ssl 0xbabecafe,%xmm5
|
||||
|
||||
// CHECK: cvtsi2ss 305419896, %xmm5
|
||||
cvtsi2ss 0x12345678,%xmm5
|
||||
// CHECK: cvtsi2ssl 305419896, %xmm5
|
||||
cvtsi2ssl 0x12345678,%xmm5
|
||||
|
||||
// CHECK: cvttps2pi 3735928559(%ebx,%ecx,8), %mm3
|
||||
cvttps2pi 0xdeadbeef(%ebx,%ecx,8),%mm3
|
||||
|
|
@ -17342,23 +17342,23 @@
|
|||
// CHECK: cvtpi2pd %mm3, %xmm5
|
||||
cvtpi2pd %mm3,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd %ecx, %xmm5
|
||||
cvtsi2sd %ecx,%xmm5
|
||||
// CHECK: cvtsi2sdl %ecx, %xmm5
|
||||
cvtsi2sdl %ecx,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2sd 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
// CHECK: cvtsi2sdl 3735928559(%ebx,%ecx,8), %xmm5
|
||||
cvtsi2sdl 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 69, %xmm5
|
||||
cvtsi2sd 0x45,%xmm5
|
||||
// CHECK: cvtsi2sdl 69, %xmm5
|
||||
cvtsi2sdl 0x45,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 32493, %xmm5
|
||||
cvtsi2sd 0x7eed,%xmm5
|
||||
// CHECK: cvtsi2sdl 32493, %xmm5
|
||||
cvtsi2sdl 0x7eed,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 3133065982, %xmm5
|
||||
cvtsi2sd 0xbabecafe,%xmm5
|
||||
// CHECK: cvtsi2sdl 3133065982, %xmm5
|
||||
cvtsi2sdl 0xbabecafe,%xmm5
|
||||
|
||||
// CHECK: cvtsi2sd 305419896, %xmm5
|
||||
cvtsi2sd 0x12345678,%xmm5
|
||||
// CHECK: cvtsi2sdl 305419896, %xmm5
|
||||
cvtsi2sdl 0x12345678,%xmm5
|
||||
|
||||
// CHECK: divpd 3735928559(%ebx,%ecx,8), %xmm5
|
||||
divpd 0xdeadbeef(%ebx,%ecx,8),%xmm5
|
||||
|
|
|
|||
|
|
@ -507,15 +507,15 @@ fsave 32493
|
|||
|
||||
// rdar://8456382 - cvtsd2si support.
|
||||
cvtsd2si %xmm1, %rax
|
||||
// CHECK: cvtsd2siq %xmm1, %rax
|
||||
// CHECK: cvtsd2si %xmm1, %rax
|
||||
// CHECK: encoding: [0xf2,0x48,0x0f,0x2d,0xc1]
|
||||
cvtsd2si %xmm1, %eax
|
||||
// CHECK: cvtsd2sil %xmm1, %eax
|
||||
// CHECK: cvtsd2si %xmm1, %eax
|
||||
// CHECK: encoding: [0xf2,0x0f,0x2d,0xc1]
|
||||
|
||||
cvtsd2siq %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
|
||||
cvtsd2sil %xmm0, %eax // CHECK: cvtsd2sil %xmm0, %eax
|
||||
cvtsd2si %xmm0, %rax // CHECK: cvtsd2siq %xmm0, %rax
|
||||
cvtsd2siq %xmm0, %rax // CHECK: cvtsd2si %xmm0, %rax
|
||||
cvtsd2sil %xmm0, %eax // CHECK: cvtsd2si %xmm0, %eax
|
||||
cvtsd2si %xmm0, %rax // CHECK: cvtsd2si %xmm0, %rax
|
||||
|
||||
|
||||
cvttpd2dq %xmm1, %xmm0 // CHECK: cvttpd2dq %xmm1, %xmm0
|
||||
|
|
|
|||
|
|
@ -1404,25 +1404,25 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
|
|||
// CHECK: encoding: [0xc5,0xfa,0x2c,0x01]
|
||||
vcvttss2si (%rcx), %eax
|
||||
|
||||
// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12
|
||||
// CHECK: vcvtsi2ssl (%rax), %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc5,0x22,0x2a,0x20]
|
||||
vcvtsi2ss (%rax), %xmm11, %xmm12
|
||||
vcvtsi2ssl (%rax), %xmm11, %xmm12
|
||||
|
||||
// CHECK: vcvtsi2ss (%rax), %xmm11, %xmm12
|
||||
// CHECK: vcvtsi2ssl (%rax), %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc5,0x22,0x2a,0x20]
|
||||
vcvtsi2ss (%rax), %xmm11, %xmm12
|
||||
vcvtsi2ssl (%rax), %xmm11, %xmm12
|
||||
|
||||
// CHECK: vcvttsd2si (%rcx), %eax
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2c,0x01]
|
||||
vcvttsd2si (%rcx), %eax
|
||||
|
||||
// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12
|
||||
// CHECK: vcvtsi2sdl (%rax), %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc5,0x23,0x2a,0x20]
|
||||
vcvtsi2sd (%rax), %xmm11, %xmm12
|
||||
vcvtsi2sdl (%rax), %xmm11, %xmm12
|
||||
|
||||
// CHECK: vcvtsi2sd (%rax), %xmm11, %xmm12
|
||||
// CHECK: vcvtsi2sdl (%rax), %xmm11, %xmm12
|
||||
// CHECK: encoding: [0xc5,0x23,0x2a,0x20]
|
||||
vcvtsi2sd (%rax), %xmm11, %xmm12
|
||||
vcvtsi2sdl (%rax), %xmm11, %xmm12
|
||||
|
||||
// CHECK: vmovaps (%rax), %xmm12
|
||||
// CHECK: encoding: [0xc5,0x78,0x28,0x20]
|
||||
|
|
@ -1512,11 +1512,11 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
|
|||
// CHECK: encoding: [0xc4,0x41,0x18,0x12,0xeb]
|
||||
vmovhlps %xmm11, %xmm12, %xmm13
|
||||
|
||||
// CHECK: vcvtss2sil %xmm11, %eax
|
||||
// CHECK: vcvtss2si %xmm11, %eax
|
||||
// CHECK: encoding: [0xc4,0xc1,0x7a,0x2d,0xc3]
|
||||
vcvtss2si %xmm11, %eax
|
||||
|
||||
// CHECK: vcvtss2sil (%rax), %ebx
|
||||
// CHECK: vcvtss2si (%rax), %ebx
|
||||
// CHECK: encoding: [0xc5,0xfa,0x2d,0x18]
|
||||
vcvtss2si (%rax), %ebx
|
||||
|
||||
|
|
@ -3860,29 +3860,29 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
|
|||
// CHECK: encoding: [0xc4,0x63,0x2d,0x06,0x18,0x07]
|
||||
vperm2f128 $7, (%rax), %ymm10, %ymm11
|
||||
|
||||
// CHECK: vcvtsd2sil %xmm8, %r8d
|
||||
// CHECK: vcvtsd2si %xmm8, %r8d
|
||||
// CHECK: encoding: [0xc4,0x41,0x7b,0x2d,0xc0]
|
||||
vcvtsd2sil %xmm8, %r8d
|
||||
vcvtsd2si %xmm8, %r8d
|
||||
|
||||
// CHECK: vcvtsd2sil (%rcx), %ecx
|
||||
// CHECK: vcvtsd2si (%rcx), %ecx
|
||||
// CHECK: encoding: [0xc5,0xfb,0x2d,0x09]
|
||||
vcvtsd2sil (%rcx), %ecx
|
||||
vcvtsd2si (%rcx), %ecx
|
||||
|
||||
// CHECK: vcvtss2siq %xmm4, %rcx
|
||||
// CHECK: vcvtss2si %xmm4, %rcx
|
||||
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2d,0xcc]
|
||||
vcvtss2siq %xmm4, %rcx
|
||||
vcvtss2si %xmm4, %rcx
|
||||
|
||||
// CHECK: vcvtss2siq (%rcx), %r8
|
||||
// CHECK: vcvtss2si (%rcx), %r8
|
||||
// CHECK: encoding: [0xc4,0x61,0xfa,0x2d,0x01]
|
||||
vcvtss2siq (%rcx), %r8
|
||||
vcvtss2si (%rcx), %r8
|
||||
|
||||
// CHECK: vcvtsi2sd %r8d, %xmm8, %xmm15
|
||||
// CHECK: vcvtsi2sdl %r8d, %xmm8, %xmm15
|
||||
// CHECK: encoding: [0xc4,0x41,0x3b,0x2a,0xf8]
|
||||
vcvtsi2sd %r8d, %xmm8, %xmm15
|
||||
vcvtsi2sdl %r8d, %xmm8, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2sd (%rbp), %xmm8, %xmm15
|
||||
// CHECK: vcvtsi2sdl (%rbp), %xmm8, %xmm15
|
||||
// CHECK: encoding: [0xc5,0x3b,0x2a,0x7d,0x00]
|
||||
vcvtsi2sd (%rbp), %xmm8, %xmm15
|
||||
vcvtsi2sdl (%rbp), %xmm8, %xmm15
|
||||
|
||||
// CHECK: vcvtsi2sdq %rcx, %xmm4, %xmm6
|
||||
// CHECK: encoding: [0xc4,0xe1,0xdb,0x2a,0xf1]
|
||||
|
|
@ -3900,21 +3900,21 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
|
|||
// CHECK: encoding: [0xc4,0xe1,0xda,0x2a,0x31]
|
||||
vcvtsi2ssq (%rcx), %xmm4, %xmm6
|
||||
|
||||
// CHECK: vcvttsd2siq %xmm4, %rcx
|
||||
// CHECK: vcvttsd2si %xmm4, %rcx
|
||||
// CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0xcc]
|
||||
vcvttsd2siq %xmm4, %rcx
|
||||
vcvttsd2si %xmm4, %rcx
|
||||
|
||||
// CHECK: vcvttsd2siq (%rcx), %rcx
|
||||
// CHECK: vcvttsd2si (%rcx), %rcx
|
||||
// CHECK: encoding: [0xc4,0xe1,0xfb,0x2c,0x09]
|
||||
vcvttsd2siq (%rcx), %rcx
|
||||
vcvttsd2si (%rcx), %rcx
|
||||
|
||||
// CHECK: vcvttss2siq %xmm4, %rcx
|
||||
// CHECK: vcvttss2si %xmm4, %rcx
|
||||
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0xcc]
|
||||
vcvttss2siq %xmm4, %rcx
|
||||
vcvttss2si %xmm4, %rcx
|
||||
|
||||
// CHECK: vcvttss2siq (%rcx), %rcx
|
||||
// CHECK: vcvttss2si (%rcx), %rcx
|
||||
// CHECK: encoding: [0xc4,0xe1,0xfa,0x2c,0x09]
|
||||
vcvttss2siq (%rcx), %rcx
|
||||
vcvttss2si (%rcx), %rcx
|
||||
|
||||
// CHECK: vlddqu (%rax), %ymm12
|
||||
// CHECK: encoding: [0xc5,0x7f,0xf0,0x20]
|
||||
|
|
|
|||
Loading…
Reference in New Issue