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[AVR] Fix useDeprecatedPositionallyEncodedOperands errors. 

This is a follow-on to https://reviews.llvm.org/D134073.

It renames a few fields to have consistent names, as well as renaming
operands to match the field names.

The encoder behavior is unchanged by this cleanup, but a few
instructions were previously being disassembled incorrectly, and have
been corrected by this change. All of the affected instructions were
missing disassembly tests, which are now added.

Differential Revision: https://reviews.llvm.org/D134185
This commit is contained in:
James Y Knight 2022-09-19 10:10:01 -04:00
parent a8c59bcc01
commit 4f188ef89c
8 changed files with 216 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/AVR/AVR.td
View File

@ -32,9 +32,7 @@ include "AVRRegisterInfo.td"
include "AVRInstrInfo.td"
def AVRInstrInfo : InstrInfo {
let useDeprecatedPositionallyEncodedOperands = true;
}
def AVRInstrInfo : InstrInfo;
//===---------------------------------------------------------------------===//
// Calling Conventions

38
llvm/lib/Target/AVR/AVRInstrFormats.td
View File

@ -134,11 +134,11 @@ class FRdK<bits<4> opcode, dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===//
class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
bits<5> rd;
let Inst{15 - 12} = opcode;
let Inst{11 - 9} = f{6 - 4};
let Inst{8 - 4} = d;
let Inst{8 - 4} = rd;
let Inst{3 - 0} = f{3 - 0};
let DecoderMethod = "decodeFRd";
@ -215,14 +215,14 @@ class FSTLD<bit type, bits<2> mode, dag outs, dag ins, string asmstr,
//===---------------------------------------------------------------------===//
class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<5> reg;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
let Inst{11 - 9} = 0b000;
let Inst{8} = reg{4};
let Inst{8} = rd{4};
let Inst{7 - 4} = reg{3 - 0};
let Inst{7 - 4} = rd{3 - 0};
let Inst{3 - 2} = 0b01;
let Inst{1} = e;
@ -239,12 +239,12 @@ class FLPMX<bit e, bit p, dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===//
class FMOVWRdRr<dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
bits<5> r;
bits<5> rd;
bits<5> rr;
let Inst{15 - 8} = 0b00000001;
let Inst{7 - 4} = d{4 - 1};
let Inst{3 - 0} = r{4 - 1};
let Inst{7 - 4} = rd{4 - 1};
let Inst{3 - 0} = rr{4 - 1};
let DecoderMethod = "decodeFMOVWRdRr";
}
@ -296,18 +296,18 @@ class FFMULRdRr<bits<2> f, dag outs, dag ins, string asmstr, list<dag> pattern>
// Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
// f = secondary opcode = 1 bit
// k = constant data = 6 bits
// d = destination = 4 bits
// d = destination = 2 bits
// (Only accepts r25:24 r27:26 r29:28 r31:30)
//===----------------------------------------------------------------------===//
class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<5> dst; // accept 5 bits but only encode bits 1 and 2
bits<5> rd; // accept 5 bits but only encode bits 1 and 2
bits<6> k;
let Inst{15 - 9} = 0b1001011;
let Inst{8} = f;
let Inst{7 - 6} = k{5 - 4};
let Inst{5 - 4} = dst{2 - 1};
let Inst{5 - 4} = rd{2 - 1};
let Inst{3 - 0} = k{3 - 0};
let DecoderMethod = "decodeFWRdK";
@ -321,12 +321,12 @@ class FWRdK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===//
class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<5> d;
bits<5> rd;
bits<6> A;
let Inst{15 - 11} = 0b10110;
let Inst{10 - 9} = A{5 - 4};
let Inst{8 - 4} = d;
let Inst{8 - 4} = rd;
let Inst{3 - 0} = A{3 - 0};
let DecoderMethod = "decodeFIORdA";
@ -341,11 +341,11 @@ class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<6> A;
bits<5> r;
bits<5> rr;
let Inst{15 - 11} = 0b10111;
let Inst{10 - 9} = A{5 - 4};
let Inst{8 - 4} = r;
let Inst{8 - 4} = rr;
let Inst{3 - 0} = A{3 - 0};
let DecoderMethod = "decodeFIOARr";
@ -360,7 +360,7 @@ class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
//===----------------------------------------------------------------------===//
class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
bits<5> A;
bits<5> addr;
bits<3> b;
let Inst{15 - 12} = 0b1001;
@ -368,9 +368,9 @@ class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{11 - 10} = 0b10;
let Inst{9 - 8} = t;
let Inst{7 - 4} = A{4 - 1};
let Inst{7 - 4} = addr{4 - 1};
let Inst{3} = A{0};
let Inst{3} = addr{0};
let Inst{2 - 0} = b{2 - 0};
let DecoderMethod = "decodeFIOBIT";

170
llvm/lib/Target/AVR/AVRInstrInfo.td
View File

@ -648,46 +648,46 @@ let isCommutable = 1, Defs = [R1, R0, SREG] in {
let usesCustomInserter = 1 in {
def MULRdRr : FRdRr<0b1001, 0b11, (outs),
(ins GPR8
: $lhs, GPR8
: $rhs),
"mul\t$lhs, $rhs",
[/*(set R1, R0, (smullohi i8:$lhs, i8:$rhs))*/]>,
: $rd, GPR8
: $rr),
"mul\t$rd, $rr",
[/*(set R1, R0, (smullohi i8:$rd, i8:$rr))*/]>,
Requires<[SupportsMultiplication]>;
def MULSRdRr : FMUL2RdRr<0, (outs),
(ins LD8
: $lhs, LD8
: $rhs),
"muls\t$lhs, $rhs", []>,
: $rd, LD8
: $rr),
"muls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
def MULSURdRr : FMUL2RdRr<1, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"mulsu\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"mulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMUL : FFMULRdRr<0b01, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmul\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmul\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMULS : FFMULRdRr<0b10, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmuls\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmuls\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
def FMULSU : FFMULRdRr<0b11, (outs),
(ins LD8lo
: $lhs, LD8lo
: $rhs),
"fmulsu\t$lhs, $rhs", []>,
: $rd, LD8lo
: $rr),
"fmulsu\t$rd, $rr", []>,
Requires<[SupportsMultiplication]>;
}
@ -948,9 +948,9 @@ def : InstAlias<"sbr\t$rd, $k",
let isBarrier = 1, isBranch = 1, isTerminator = 1 in {
def RJMPk : FBRk<0, (outs),
(ins brtarget_13
: $target),
"rjmp\t$target", [(br bb
: $target)]>;
: $k),
"rjmp\t$k", [(br bb
: $k)]>;
let isIndirectBranch = 1,
Uses = [R31R30] in def IJMP
@ -1095,27 +1095,27 @@ let isBranch = 1, isTerminator = 1 in {
let isBarrier = 1 in {
def SBRCRrB : FRdB<0b10, (outs),
(ins GPR8
: $rr, i8imm
: $rd, i8imm
: $b),
"sbrc\t$rr, $b", []>;
"sbrc\t$rd, $b", []>;
def SBRSRrB : FRdB<0b11, (outs),
(ins GPR8
: $rr, i8imm
: $rd, i8imm
: $b),
"sbrs\t$rr, $b", []>;
"sbrs\t$rd, $b", []>;
def SBICAb : FIOBIT<0b01, (outs),
(ins imm_port5
: $a, i8imm
: $addr, i8imm
: $b),
"sbic\t$a, $b", []>;
"sbic\t$addr, $b", []>;
def SBISAb : FIOBIT<0b11, (outs),
(ins imm_port5
: $a, i8imm
: $addr, i8imm
: $b),
"sbis\t$a, $b", []>;
"sbis\t$addr, $b", []>;
}
// Relative branches on status flag bits.
@ -1186,51 +1186,51 @@ def : InstAlias<"brid\t$k", (BRBCsk 7, relbrtarget_7 : $k)>;
let isBranch = 1, isTerminator = 1, Uses = [SREG] in {
def BREQk : FBRsk<0, 0b001, (outs),
(ins relbrtarget_7
: $target),
"breq\t$target", [(AVRbrcond bb
: $target, AVR_COND_EQ)]>;
: $k),
"breq\t$k", [(AVRbrcond bb
: $k, AVR_COND_EQ)]>;
def BRNEk : FBRsk<1, 0b001, (outs),
(ins relbrtarget_7
: $target),
"brne\t$target", [(AVRbrcond bb
: $target, AVR_COND_NE)]>;
: $k),
"brne\t$k", [(AVRbrcond bb
: $k, AVR_COND_NE)]>;
def BRSHk : FBRsk<1, 0b000, (outs),
(ins relbrtarget_7
: $target),
"brsh\t$target", [(AVRbrcond bb
: $target, AVR_COND_SH)]>;
: $k),
"brsh\t$k", [(AVRbrcond bb
: $k, AVR_COND_SH)]>;
def BRLOk : FBRsk<0, 0b000, (outs),
(ins relbrtarget_7
: $target),
"brlo\t$target", [(AVRbrcond bb
: $target, AVR_COND_LO)]>;
: $k),
"brlo\t$k", [(AVRbrcond bb
: $k, AVR_COND_LO)]>;
def BRMIk : FBRsk<0, 0b010, (outs),
(ins relbrtarget_7
: $target),
"brmi\t$target", [(AVRbrcond bb
: $target, AVR_COND_MI)]>;
: $k),
"brmi\t$k", [(AVRbrcond bb
: $k, AVR_COND_MI)]>;
def BRPLk : FBRsk<1, 0b010, (outs),
(ins relbrtarget_7
: $target),
"brpl\t$target", [(AVRbrcond bb
: $target, AVR_COND_PL)]>;
: $k),
"brpl\t$k", [(AVRbrcond bb
: $k, AVR_COND_PL)]>;
def BRGEk : FBRsk<1, 0b100, (outs),
(ins relbrtarget_7
: $target),
"brge\t$target", [(AVRbrcond bb
: $target, AVR_COND_GE)]>;
: $k),
"brge\t$k", [(AVRbrcond bb
: $k, AVR_COND_GE)]>;
def BRLTk : FBRsk<0, 0b100, (outs),
(ins relbrtarget_7
: $target),
"brlt\t$target", [(AVRbrcond bb
: $target, AVR_COND_LT)]>;
: $k),
"brlt\t$k", [(AVRbrcond bb
: $k, AVR_COND_LT)]>;
}
//===----------------------------------------------------------------------===//
@ -1246,10 +1246,10 @@ let hasSideEffects = 0 in {
"mov\t$rd, $rr", []>;
def MOVWRdRr : FMOVWRdRr<(outs DREGS
: $dst),
: $rd),
(ins DREGS
: $src),
"movw\t$dst, $src", []>,
: $rr),
"movw\t$rd, $rr", []>,
Requires<[HasMOVW]>;
}
@ -1657,20 +1657,20 @@ let canFoldAsLoad = 1, isReMaterializable = 1, mayLoad = 1,
def LPMRdZ : FLPMX<0, 0,
(outs GPR8
: $dst),
: $rd),
(ins ZREG
: $z),
"lpm\t$dst, $z", []>,
"lpm\t$rd, $z", []>,
Requires<[HasLPMX]>;
// Load program memory, while postincrementing the Z register.
let Defs = [R31R30] in {
def LPMRdZPi : FLPMX<0, 1,
(outs GPR8
: $dst),
: $rd),
(ins ZREG
: $z),
"lpm\t$dst, $z+", []>,
"lpm\t$rd, $z+", []>,
Requires<[HasLPMX]>;
def LPMWRdZ : Pseudo<(outs DREGS
@ -1696,13 +1696,13 @@ let mayLoad = 1, hasSideEffects = 0 in {
: F16<0b1001010111011000, (outs), (ins), "elpm", []>,
Requires<[HasELPM]>;
def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$dst), (ins ZREG:$z),
"elpm\t$dst, $z", []>,
def ELPMRdZ : FLPMX<1, 0, (outs GPR8:$rd), (ins ZREG:$z),
"elpm\t$rd, $z", []>,
Requires<[HasELPMX]>;
let Defs = [R31R30] in {
def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$dst), (ins ZREG:$z),
"elpm\t$dst, $z+", []>,
def ELPMRdZPi : FLPMX<1, 1, (outs GPR8:$rd), (ins ZREG:$z),
"elpm\t$rd, $z+", []>,
Requires<[HasELPMX]>;
}
@ -1742,12 +1742,12 @@ let Uses = [R1, R0] in {
// Read data from IO location operations.
let canFoldAsLoad = 1, isReMaterializable = 1 in {
def INRdA : FIORdA<(outs GPR8
: $dst),
: $rd),
(ins imm_port6
: $src),
"in\t$dst, $src", [(set i8
: $dst, (load ioaddr8
: $src))]>;
: $A),
"in\t$rd, $A", [(set i8
: $rd, (load ioaddr8
: $A))]>;
def INWRdA : Pseudo<(outs DREGS
: $dst),
@ -1761,11 +1761,11 @@ let canFoldAsLoad = 1, isReMaterializable = 1 in {
// Write data to IO location operations.
def OUTARr : FIOARr<(outs),
(ins imm_port6
: $dst, GPR8
: $src),
"out\t$dst, $src", [(store i8
: $src, ioaddr8
: $dst)]>;
: $A, GPR8
: $rr),
"out\t$A, $rr", [(store i8
: $rr, ioaddr8
: $A)]>;
def OUTWARr : Pseudo<(outs),
(ins imm_port6
@ -1781,8 +1781,8 @@ let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
let mayStore = 1 in {
def PUSHRr : FRd<0b1001, 0b0011111, (outs),
(ins GPR8
: $reg),
"push\t$reg", []>,
: $rd),
"push\t$rd", []>,
Requires<[HasSRAM]>;
def PUSHWRr : Pseudo<(outs),
@ -1796,8 +1796,8 @@ let Defs = [SP], Uses = [SP], hasSideEffects = 0 in {
let mayLoad = 1 in {
def POPRd : FRd<0b1001, 0b0001111,
(outs GPR8
: $reg),
(ins), "pop\t$reg", []>,
: $rd),
(ins), "pop\t$rd", []>,
Requires<[HasSRAM]>;
def POPWRd : Pseudo<(outs DREGS
@ -2060,22 +2060,22 @@ let Constraints =
def SBIAb : FIOBIT<0b10, (outs),
(ins imm_port5
: $addr, i8imm
: $bit),
"sbi\t$addr, $bit", [(store(or(i8(load lowioaddr8
: $b),
"sbi\t$addr, $b", [(store(or(i8(load lowioaddr8
: $addr)),
iobitpos8
: $bit),
: $b),
lowioaddr8
: $addr)]>;
def CBIAb : FIOBIT<0b00, (outs),
(ins imm_port5
: $addr, i8imm
: $bit),
"cbi\t$addr, $bit", [(store(and(i8(load lowioaddr8
: $b),
"cbi\t$addr, $b", [(store(and(i8(load lowioaddr8
: $addr)),
iobitposn8
: $bit),
: $b),
lowioaddr8
: $addr)]>;

87
llvm/test/MC/AVR/inst-family-cond-branch.s
View File

@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s
foo:
@ -17,6 +19,12 @@ foo:
; CHECK: brbs 1, baz ; encoding: [0bAAAAA001,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: baz, kind: fixup_7_pcrel
; INST-LABEL: <foo>:
; INST: breq .+0
; INST: breq .+0
; INST: breq .+0
; INST: breq .+0
; BRNE
brne .+10
brne .+2
@ -32,6 +40,11 @@ foo:
; CHECK: brbc 1, bar ; encoding: [0bAAAAA001,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: bar, kind: fixup_7_pcrel
; INST: brne .+0
; INST: brne .+0
; INST: brne .+0
; INST: brne .+0
bar:
; BRCS
brcs .+8
@ -48,6 +61,12 @@ bar:
; CHECK: brcs end ; encoding: [0bAAAAA000,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST-LABEL: <bar>:
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0
; BRCC
brcc .+66
brcc .-22
@ -63,7 +82,12 @@ bar:
; CHECK: brcc baz ; encoding: [0bAAAAA000,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: baz, kind: fixup_7_pcrel
; BRSH
; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0
; BRSH
brsh .+32
brsh .+70
brsh car
@ -75,6 +99,10 @@ bar:
; CHECK: brsh car ; encoding: [0bAAAAA000,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel
; INST: brsh .+0
; INST: brsh .+0
; INST: brsh .+0
baz:
; BRLO
@ -89,6 +117,11 @@ baz:
; CHECK: brlo car ; encoding: [0bAAAAA000,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel
; INST-LABEL: <baz>:
; INST: brlo .+0
; INST: brlo .+0
; INST: brlo .+0
; BRMI
brmi .+66
brmi .+58
@ -101,6 +134,10 @@ baz:
; CHECK: brmi car ; encoding: [0bAAAAA010,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel
; INST: brmi .+0
; INST: brmi .+0
; INST: brmi .+0
; BRPL
brpl .-12
brpl .+18
@ -113,7 +150,11 @@ baz:
; CHECK: brpl car ; encoding: [0bAAAAA010,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel
; BRGE
; INST: brpl .+0
; INST: brpl .+0
; INST: brpl .+0
; BRGE
brge .+50
brge .+42
brge car
@ -125,6 +166,10 @@ baz:
; CHECK: brge car ; encoding: [0bAAAAA100,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: car, kind: fixup_7_pcrel
; INST: brge .+0
; INST: brge .+0
; INST: brge .+0
car:
; BRLT
brlt .+16
@ -138,6 +183,11 @@ car:
; CHECK: brlt end ; encoding: [0bAAAAA100,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST-LABEL: <car>:
; INST: brlt .+0
; INST: brlt .+0
; INST: brlt .+0
; BRHS
brhs .-66
brhs .+14
@ -150,6 +200,10 @@ car:
; CHECK: brhs just_another_label ; encoding: [0bAAAAA101,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
; INST: brhs .+0
; INST: brhs .+0
; INST: brhs .+0
; BRHC
brhc .+12
brhc .+14
@ -162,6 +216,10 @@ car:
; CHECK: brhc just_another_label ; encoding: [0bAAAAA101,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
; INST: brhc .+0
; INST: brhc .+0
; INST: brhc .+0
; BRTS
brts .+18
brts .+22
@ -174,6 +232,10 @@ car:
; CHECK: brts just_another_label ; encoding: [0bAAAAA110,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: just_another_label, kind: fixup_7_pcrel
; INST: brts .+0
; INST: brts .+0
; INST: brts .+0
just_another_label:
; BRTC
brtc .+52
@ -187,6 +249,11 @@ just_another_label:
; CHECK: brtc end ; encoding: [0bAAAAA110,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST-LABEL: <just_another_label>:
; INST: brtc .+0
; INST: brtc .+0
; INST: brtc .+0
; BRVS
brvs .+18
brvs .+32
@ -199,6 +266,10 @@ just_another_label:
; CHECK: brvs end ; encoding: [0bAAAAA011,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST: brvs .+0
; INST: brvs .+0
; INST: brvs .+0
; BRVC
brvc .-28
brvc .-62
@ -211,6 +282,10 @@ just_another_label:
; CHECK: brvc end ; encoding: [0bAAAAA011,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST: brvc .+0
; INST: brvc .+0
; INST: brvc .+0
; BRIE
brie .+20
brie .+40
@ -223,6 +298,10 @@ just_another_label:
; CHECK: brie end ; encoding: [0bAAAAA111,0b111100AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST: brie .+0
; INST: brie .+0
; INST: brie .+0
; BRID
brid .+42
brid .+62
@ -235,4 +314,8 @@ just_another_label:
; CHECK: brid end ; encoding: [0bAAAAA111,0b111101AA]
; CHECK: ; fixup A - offset: 0, value: end, kind: fixup_7_pcrel
; INST: brid .+0
; INST: brid .+0
; INST: brid .+0
end:

7
llvm/test/MC/AVR/inst-mul.s
View File

@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s \
; RUN: | llvm-objdump -d --mattr=mul - | FileCheck --check-prefix=INST %s
foo:
@ -11,3 +13,8 @@ foo:
; CHECK: mul r15, r0 ; encoding: [0xf0,0x9c]
; CHECK: mul r16, r31 ; encoding: [0x0f,0x9f]
; CHECK: mul r31, r16 ; encoding: [0xf0,0x9f]
; INST: mul r0, r15
; INST: mul r15, r0
; INST: mul r16, r31
; INST: mul r31, r16

11
llvm/test/MC/AVR/inst-rjmp.s
View File

@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s
foo:
@ -29,3 +31,12 @@ end:
; CHECK: ; fixup A - offset: 0, value: .Ltmp4-4, kind: fixup_13_pcrel
; CHECK: rjmp .Ltmp5-6 ; encoding: [A,0b1100AAAA]
; CHECK: ; fixup A - offset: 0, value: .Ltmp5-6, kind: fixup_13_pcrel
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0
; INST: rjmp .+0

4
llvm/test/MC/AVR/inst-sbrc.s
View File

@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s
foo:
@ -9,3 +11,5 @@ foo:
; CHECK: sbrc r2, 3 ; encoding: [0x23,0xfc]
; CHECK: sbrc r0, 7 ; encoding: [0x07,0xfc]
; INST: sbrc r2, 3
; INST: sbrc r0, 7

4
llvm/test/MC/AVR/inst-sbrs.s
View File

@ -1,4 +1,6 @@
; RUN: llvm-mc -triple avr -show-encoding < %s | FileCheck %s
; RUN: llvm-mc -filetype=obj -triple avr < %s \
; RUN: | llvm-objdump -d - | FileCheck --check-prefix=INST %s
foo:
@ -9,3 +11,5 @@ foo:
; CHECK: sbrs r2, 3 ; encoding: [0x23,0xfe]
; CHECK: sbrs r0, 7 ; encoding: [0x07,0xfe]
; INST: sbrs r2, 3
; INST: sbrs r0, 7