forked from OSchip/llvm-project
[LegalizeDAG] Handle NeedInvert when expanding BR_CC
This is a follow-up fix to commit03c8d6a0c4
. Seems like we now end up with NeedInvert being set in the result from LegalizeSetCCCondCode more often than in the past, so we need to handle NeedInvert when expanding BR_CC. Not sure how to deal with the "Tmp4.getNode()" case properly, but current assumption is that that code path isn't impacted by the changes in03c8d6a0c4
so we can simply move the old assert into the if-branch and only handle NeedInvert in the else-branch. I think that the test case added here, for PowerPC, might have failed also before commit03c8d6a0c4
. But we started to hit the assert more often downstream when having merged that commit. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94762
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@ -3966,16 +3966,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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(void)Legalized;
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assert(Legalized && "Can't legalize BR_CC with legal condition!");
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assert(!NeedInvert && "Don't know how to invert BR_CC!");
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// If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
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// node.
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if (Tmp4.getNode()) {
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assert(!NeedInvert && "Don't know how to invert BR_CC!");
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
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Tmp4, Tmp2, Tmp3, Node->getOperand(4));
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} else {
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Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
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Tmp4 = DAG.getCondCode(ISD::SETNE);
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Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE);
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Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
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Tmp2, Tmp3, Node->getOperand(4));
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}
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@ -0,0 +1,33 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O1 -mtriple powerpc -mattr=+spe -o - %s | FileCheck %s
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; This used to hit an assert
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;
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; ../lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3971: bool {anonymous}::SelectionDAGLegalize::ExpandNode(llvm::SDNode*): Assertion `!NeedInvert && "Don't know how to invert BR_CC!"' failed.
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define void @test_fcmpueq_legalize_br_cc_with_invert(float %a) {
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; CHECK-LABEL: test_fcmpueq_legalize_br_cc_with_invert:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 4, .LCPI0_0@ha
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; CHECK-NEXT: lwz 4, .LCPI0_0@l(4)
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; CHECK-NEXT: .LBB0_1: # %l1
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; CHECK-NEXT: #
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; CHECK-NEXT: efscmplt 7, 3, 4
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; CHECK-NEXT: efscmpgt 0, 3, 4
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; CHECK-NEXT: mfcr 5 # cr7
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; CHECK-NEXT: mcrf 7, 0
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; CHECK-NEXT: mfcr 6 # cr7
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; CHECK-NEXT: rlwinm 5, 5, 30, 31, 31
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; CHECK-NEXT: rlwinm 6, 6, 30, 31, 31
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; CHECK-NEXT: or. 5, 6, 5
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; CHECK-NEXT: beq 0, .LBB0_1
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; CHECK-NEXT: # %bb.2: # %l2
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; CHECK-NEXT: blr
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entry:
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br label %l1
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l1:
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%fcmp = fcmp ueq float %a, 0xC6306B3440000000
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br i1 %fcmp, label %l1, label %l2
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l2:
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ret void
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}
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