forked from OSchip/llvm-project
Added custom SELECT_CC lowering
Added special isel for ADDE,SUBE and new patterns to match SUBC,ADDC llvm-svn: 52031
This commit is contained in:
Bruno Cardoso Lopes
parent
1d304a99d7
commit
4eed3afda0
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@ -226,6 +226,52 @@ Select(SDOperand N)
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default: break;
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case ISD::ADDE: {
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// ADDE is usally attached with a ADDC instruction, we must
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// compare ADDC operands and set a register if we have a carry.
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SDOperand InFlag = Node->getOperand(2);
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unsigned Opc = InFlag.getOpcode();
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assert((Opc == ISD::ADDC || Opc == ISD::ADDE) &&
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"ADDE flag operand must come from a ADDC or ADDE");
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SDOperand Ops[] = { InFlag.getValue(0), InFlag.getOperand(1) };
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SDOperand LHS = Node->getOperand(0);
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SDOperand RHS = Node->getOperand(1);
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AddToISelQueue(LHS);
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AddToISelQueue(RHS);
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MVT::ValueType VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
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SDOperand(Carry,0), RHS);
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return CurDAG->SelectNodeTo(N.Val, Mips::ADDu, VT, MVT::Flag,
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LHS, SDOperand(AddCarry,0));
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}
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case ISD::SUBE: {
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// SUBE is usally attached with a SUBC instruction, we must
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// compare SUBC operands and set a register if we have a carry.
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SDOperand InFlag = Node->getOperand(2);
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unsigned Opc = InFlag.getOpcode();
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assert((Opc == ISD::SUBC || Opc == ISD::SUBE) &&
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"SUBE flag operand must come from a SUBC or SUBE");
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SDOperand Ops[] = { InFlag.getOperand(0), InFlag.getOperand(1) };
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SDOperand LHS = Node->getOperand(0);
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SDOperand RHS = Node->getOperand(1);
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AddToISelQueue(LHS);
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AddToISelQueue(RHS);
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MVT::ValueType VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, VT,
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SDOperand(Carry,0), RHS);
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return CurDAG->SelectNodeTo(N.Val, Mips::SUBu, VT, MVT::Flag,
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LHS, SDOperand(AddCarry,0));
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}
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/// Special Mul operations
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case ISD::MULHS:
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case ISD::MULHU: {
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@ -39,11 +39,12 @@ getTargetNodeName(unsigned Opcode) const
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{
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switch (Opcode)
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{
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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default : return NULL;
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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default : return NULL;
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}
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}
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@ -65,6 +66,7 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
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// Load extented operations for i1 types must be promoted
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setLoadXAction(ISD::EXTLOAD, MVT::i1, Promote);
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@ -75,7 +77,6 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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@ -124,10 +125,75 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG)
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case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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}
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return SDOperand();
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}
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MachineBasicBlock *
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MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB)
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{
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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switch (MI->getOpcode()) {
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default: assert(false && "Unexpected instr type to insert");
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case Mips::Select_CC: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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// diamond control-flow pattern. The incoming instruction knows the
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// destination vreg to set, the condition code register to branch on, the
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// true/false values to select between, and a branch opcode to use.
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const BasicBlock *LLVM_BB = BB->getBasicBlock();
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ilist<MachineBasicBlock>::iterator It = BB;
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++It;
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// thisMBB:
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// ...
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// TrueVal = ...
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// setcc r1, r2, r3
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// bNE r1, r0, copy1MBB
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// fallthrough --> copy0MBB
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MachineBasicBlock *thisMBB = BB;
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MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
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MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
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BuildMI(BB, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
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.addReg(Mips::ZERO).addMBB(sinkMBB);
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MachineFunction *F = BB->getParent();
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F->getBasicBlockList().insert(It, copy0MBB);
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F->getBasicBlockList().insert(It, sinkMBB);
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// Update machine-CFG edges by first adding all successors of the current
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// block to the new block which will contain the Phi node for the select.
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for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
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e = BB->succ_end(); i != e; ++i)
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sinkMBB->addSuccessor(*i);
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// Next, remove all successors of the current block, and add the true
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// and fallthrough blocks as its successors.
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while(!BB->succ_empty())
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BB->removeSuccessor(BB->succ_begin());
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BB->addSuccessor(copy0MBB);
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BB->addSuccessor(sinkMBB);
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// copy0MBB:
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// %FalseValue = ...
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// # fallthrough to sinkMBB
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BB = copy0MBB;
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// Update machine-CFG edges
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BB->addSuccessor(sinkMBB);
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// sinkMBB:
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// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
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// ...
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BB = sinkMBB;
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BuildMI(BB, TII->get(Mips::PHI), MI->getOperand(0).getReg())
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.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
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.addReg(MI->getOperand(3).getReg()).addMBB(thisMBB);
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delete MI; // The pseudo instruction is gone now.
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return BB;
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}
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}
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}
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//===----------------------------------------------------------------------===//
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// Lower helper functions
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//===----------------------------------------------------------------------===//
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@ -181,6 +247,23 @@ LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG)
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return SDOperand(); // Not reached
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}
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SDOperand MipsTargetLowering::
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LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG)
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{
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SDOperand LHS = Op.getOperand(0);
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SDOperand RHS = Op.getOperand(1);
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SDOperand True = Op.getOperand(2);
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SDOperand False = Op.getOperand(3);
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SDOperand CC = Op.getOperand(4);
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const MVT::ValueType *VTs = DAG.getNodeValueTypes(MVT::i32);
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SDOperand Ops[] = { LHS, RHS, CC };
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SDOperand SetCCRes = DAG.getNode(ISD::SETCC, VTs, 1, Ops, 3);
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return DAG.getNode(MipsISD::SelectCC, True.getValueType(),
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SetCCRes, True, False);
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}
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SDOperand MipsTargetLowering::
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LowerJumpTable(SDOperand Op, SelectionDAG &DAG)
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{
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@ -37,6 +37,9 @@ namespace llvm {
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// No relation with Mips Lo register
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Lo,
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// Select CC Pseudo Instruction
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SelectCC,
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// Return
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Ret
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};
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@ -80,6 +83,10 @@ namespace llvm {
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SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
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virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB);
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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@ -43,7 +43,7 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
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}
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// Mips Pseudo Instructions Format
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class PseudoInstMips<dag outs, dag ins, string asmstr, list<dag> pattern>:
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class MipsPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
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//===----------------------------------------------------------------------===//
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@ -43,6 +43,11 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// Select CC
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def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
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def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
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//===----------------------------------------------------------------------===//
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// Mips Instruction Predicate Definitions.
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//===----------------------------------------------------------------------===//
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@ -346,10 +351,10 @@ class EffectiveAddress<string instr_asm> :
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// As stack alignment is always done with addiu, we need a 16-bit immediate
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let Defs = [SP], Uses = [SP] in {
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def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
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def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>;
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def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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"!ADJCALLSTACKUP $amt1",
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[(callseq_end imm:$amt1, imm:$amt2)]>;
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}
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@ -358,10 +363,22 @@ def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
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// directives. If the real instructions corresponding these directives
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// are used, we have the same behavior, but get also a bunch of warnings
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// from the assembler.
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def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
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".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>;
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def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
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".cprestore $loc\n", []>;
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def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$reg),
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".set noreorder\n\t.cpload $reg\n\t.set reorder\n",
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[]>;
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def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc),
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".cprestore $loc\n", []>;
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// The supported Mips ISAs dont have any instruction close to the SELECT_CC
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// operation. The solution is to create a Mips pseudo SELECT_CC instruction
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// (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
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// replace it for real supported nodes into EmitInstrWithCustomInserter
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let usesCustomDAGSchedInserter = 1 in {
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def Select_CC : MipsPseudo<(outs CPURegs:$dst),
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(ins CPURegs:$CmpRes, CPURegs:$T, CPURegs:$F), "# MipsSelect_CC",
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[(set CPURegs:$dst, (MipsSelectCC CPURegs:$CmpRes,
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CPURegs:$T, CPURegs:$F))]>;
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}
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//===----------------------------------------------------------------------===//
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// Instruction definition
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@ -502,6 +519,14 @@ def : Pat<(i32 immZExt16:$in),
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def : Pat<(i32 imm:$imm),
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(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
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// Carry patterns
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def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
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(SUBu CPURegs:$lhs, CPURegs:$rhs)>;
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def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
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(ADDu CPURegs:$lhs, CPURegs:$rhs)>;
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def : Pat<(addc CPURegs:$src, imm:$imm),
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(ADDiu CPURegs:$src, imm:$imm)>;
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// Call
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def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
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(JAL tglobaladdr:$dst)>;
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@ -529,7 +554,7 @@ def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
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def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
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def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
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// some peepholes
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// peepholes
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def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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///
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