forked from OSchip/llvm-project
Fix epic bug with invalid regclass for R0D
llvm-svn: 75956
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@ -144,7 +144,7 @@ def : SubRegSet<5, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
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/// Register classes
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def GR32 : RegisterClass<"SystemZ", [i32], 32,
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// Volatile registers
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[R0D, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
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[R0W, R1W, R2W, R3W, R4W, R5W, R6W, R7W, R8W, R9W, R10W, R12W, R13W,
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// Frame pointer, sometimes allocable
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R11W,
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// Volatile, but not allocable
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