forked from OSchip/llvm-project
[AMDGPU] Only match correct type for a16
Addresses are floats when a sampler is present and unsigned integers when no sampler is present. Therefore, only zext instructions, not sext instructions should match. Also match integer constants that can be truncated. Differential Revision: https://reviews.llvm.org/D118043
This commit is contained in:
Sebastian Neubauer
parent
7cc3e141d7
commit
4ed7c6eec9
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@ -58,24 +58,37 @@ static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1,
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// Check if a value can be converted to a 16-bit value without losing
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// precision.
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static bool canSafelyConvertTo16Bit(Value &V) {
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// The value is expected to be either a float (IsFloat = true) or an unsigned
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// integer (IsFloat = false).
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static bool canSafelyConvertTo16Bit(Value &V, bool IsFloat) {
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Type *VTy = V.getType();
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if (VTy->isHalfTy() || VTy->isIntegerTy(16)) {
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// The value is already 16-bit, so we don't want to convert to 16-bit again!
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return false;
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}
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if (ConstantFP *ConstFloat = dyn_cast<ConstantFP>(&V)) {
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// We need to check that if we cast the index down to a half, we do not lose
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// precision.
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APFloat FloatValue(ConstFloat->getValueAPF());
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bool LosesInfo = true;
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FloatValue.convert(APFloat::IEEEhalf(), APFloat::rmTowardZero, &LosesInfo);
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return !LosesInfo;
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if (IsFloat) {
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if (ConstantFP *ConstFloat = dyn_cast<ConstantFP>(&V)) {
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// We need to check that if we cast the index down to a half, we do not
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// lose precision.
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APFloat FloatValue(ConstFloat->getValueAPF());
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bool LosesInfo = true;
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FloatValue.convert(APFloat::IEEEhalf(), APFloat::rmTowardZero,
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&LosesInfo);
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return !LosesInfo;
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}
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} else {
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if (ConstantInt *ConstInt = dyn_cast<ConstantInt>(&V)) {
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// We need to check that if we cast the index down to an i16, we do not
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// lose precision.
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APInt IntValue(ConstInt->getValue());
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return IntValue.getActiveBits() <= 16;
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}
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}
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Value *CastSrc;
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if (match(&V, m_FPExt(PatternMatch::m_Value(CastSrc))) ||
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match(&V, m_SExt(PatternMatch::m_Value(CastSrc))) ||
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match(&V, m_ZExt(PatternMatch::m_Value(CastSrc)))) {
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bool IsExt = IsFloat ? match(&V, m_FPExt(PatternMatch::m_Value(CastSrc)))
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: match(&V, m_ZExt(PatternMatch::m_Value(CastSrc)));
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if (IsExt) {
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Type *CastSrcTy = CastSrc->getType();
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if (CastSrcTy->isHalfTy() || CastSrcTy->isIntegerTy(16))
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return true;
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@ -203,6 +216,10 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
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if (!ST->hasA16() && !ST->hasG16())
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return None;
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// Address is interpreted as float if the instruction has a sampler or as
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// unsigned int if there is no sampler.
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bool HasSampler =
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AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode)->Sampler;
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bool FloatCoord = false;
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// true means derivatives can be converted to 16 bit, coordinates not
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bool OnlyDerivatives = false;
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@ -211,7 +228,7 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
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OperandIndex < ImageDimIntr->VAddrEnd; OperandIndex++) {
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Value *Coord = II.getOperand(OperandIndex);
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// If the values are not derived from 16-bit values, we cannot optimize.
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if (!canSafelyConvertTo16Bit(*Coord)) {
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if (!canSafelyConvertTo16Bit(*Coord, HasSampler)) {
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if (OperandIndex < ImageDimIntr->CoordStart ||
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ImageDimIntr->GradientStart == ImageDimIntr->CoordStart) {
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return None;
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@ -232,7 +249,9 @@ simplifyAMDGCNImageIntrinsic(const GCNSubtarget *ST,
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// Check if there is a bias parameter and if it can be converted to f16
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if (!OnlyDerivatives && ImageDimIntr->NumBiasArgs != 0) {
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Value *Bias = II.getOperand(ImageDimIntr->BiasIndex);
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if (!canSafelyConvertTo16Bit(*Bias))
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assert(HasSampler &&
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"Only image instructions with a sampler can have a bias");
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if (!canSafelyConvertTo16Bit(*Bias, HasSampler))
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OnlyDerivatives = true;
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}
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@ -3667,6 +3667,105 @@ define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_V2(<2 x float> addrspa
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_const(<2 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %slice) {
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; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_const(
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; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f16(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], half [[S:%.*]], half 0xH3400, half [[SLICE:%.*]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <2 x float> [[RES]], <2 x float> addrspace(1)* [[OUT:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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%dsdh32 = fpext half %dsdh to float
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%dtdh32 = fpext half %dtdh to float
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%dsdv32 = fpext half %dsdv to float
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%dtdv32 = fpext half %dtdv to float
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%s32 = fpext half %s to float
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%slice32 = fpext half %slice to float
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%res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float 0.25, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <2 x float> %res, <2 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_sample_a16_c_d_o_2darray_const_noopt(<2 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, half %dsdh, half %dtdh, half %dsdv, half %dtdv, half %s, half %slice) {
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; CHECK-LABEL: @image_sample_a16_c_d_o_2darray_const_noopt(
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; CHECK-NEXT: [[S32:%.*]] = fpext half [[S:%.*]] to float
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; CHECK-NEXT: [[SLICE32:%.*]] = fpext half [[SLICE:%.*]] to float
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; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f16.f32(i32 6, i32 [[OFFSET:%.*]], float [[ZCOMPARE:%.*]], half [[DSDH:%.*]], half [[DTDH:%.*]], half [[DSDV:%.*]], half [[DTDV:%.*]], float [[S32]], float 1.000000e+10, float [[SLICE32]], <8 x i32> [[RSRC:%.*]], <4 x i32> [[SAMP:%.*]], i1 false, i32 0, i32 0)
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; CHECK-NEXT: store <2 x float> [[RES]], <2 x float> addrspace(1)* [[OUT:%.*]], align 8
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; CHECK-NEXT: ret void
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;
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%dsdh32 = fpext half %dsdh to float
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%dtdh32 = fpext half %dtdh to float
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%dsdv32 = fpext half %dsdv to float
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%dtdv32 = fpext half %dtdv to float
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%s32 = fpext half %s to float
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%slice32 = fpext half %slice to float
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%res = call <2 x float> @llvm.amdgcn.image.sample.c.d.o.2darray.v2f32.f32.f32(i32 6, i32 %offset, float %zcompare, float %dsdh32, float %dtdh32, float %dsdv32, float %dtdv32, float %s32, float 1.0e+10, float %slice32, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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store <2 x float> %res, <2 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_load_a16_mip_1d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i16 %s) {
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; CHECK-LABEL: @image_load_a16_mip_1d(
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 [[S:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = zext i16 %s to i32
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%res = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_load_a16_mip_1d_noopt(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i16 %s) {
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; CHECK-LABEL: @image_load_a16_mip_1d_noopt(
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; CHECK-NEXT: [[S32:%.*]] = sext i16 [[S:%.*]] to i32
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 [[S32]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = sext i16 %s to i32
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%res = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i32(i32 15, i32 %s32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_load_a16_mip_2d(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i16 %s, i16 %t) {
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; CHECK-LABEL: @image_load_a16_mip_2d(
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 [[S:%.*]], i16 [[T:%.*]], <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = zext i16 %s to i32
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%t32 = zext i16 %t to i32
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%res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s32, i32 %t32, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_load_a16_mip_2d_const(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i16 %s) {
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; CHECK-LABEL: @image_load_a16_mip_2d_const(
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 [[S:%.*]], i16 -1, <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = zext i16 %s to i32
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%res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s32, i32 65535, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @image_load_a16_mip_2d_const_noopt(<4 x float> addrspace(1)* %out, <8 x i32> inreg %rsrc, i16 %s) {
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; CHECK-LABEL: @image_load_a16_mip_2d_const_noopt(
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; CHECK-NEXT: [[S32:%.*]] = zext i16 [[S:%.*]] to i32
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; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 [[S32]], i32 65536, <8 x i32> [[RSRC:%.*]], i32 0, i32 0)
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; CHECK-NEXT: store <4 x float> [[RES]], <4 x float> addrspace(1)* [[OUT:%.*]], align 16
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; CHECK-NEXT: ret void
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;
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%s32 = zext i16 %s to i32
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%res = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i32(i32 15, i32 %s32, i32 65536, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
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store <4 x float> %res, <4 x float> addrspace(1)* %out
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ret void
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}
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; --------------------------------------------------------------------
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; llvm.amdgcn.image.sample g16
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; --------------------------------------------------------------------
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