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[AArch64] Handle lowering lround on windows, where long is 32 bit 

Differential Revision: https://reviews.llvm.org/D62108

llvm-svn: 361192
This commit is contained in:
Martin Storsjo 2019-05-20 19:53:28 +00:00
parent 80efcdcdf8
commit 4ed18e5ef5
2 changed files with 48 additions and 0 deletions
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4
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@ -3083,6 +3083,10 @@ defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
def : Pat<(i32 (lround f32:$Rn)),
(!cast<Instruction>(FCVTASUWSr) f32:$Rn)>;
def : Pat<(i32 (lround f64:$Rn)),
(!cast<Instruction>(FCVTASUWDr) f64:$Rn)>;
def : Pat<(i64 (lround f32:$Rn)),
(!cast<Instruction>(FCVTASUXSr) f32:$Rn)>;
def : Pat<(i64 (lround f64:$Rn)),

44
llvm/test/CodeGen/AArch64/lround-conv-win.ll Normal file
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@ -0,0 +1,44 @@
; RUN: llc < %s -mtriple=aarch64-windows -mattr=+neon | FileCheck %s
; CHECK-LABEL: testmsxs:
; CHECK: fcvtas w8, s0
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
define i64 @testmsxs(float %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
; CHECK-LABEL: testmsws:
; CHECK: fcvtas w0, s0
; CHECK-NEXT: ret
define i32 @testmsws(float %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f32(float %x)
ret i32 %0
}
; CHECK-LABEL: testmsxd:
; CHECK: fcvtas w8, d0
; CHECK-NEXT: sxtw x0, w8
; CHECK-NEXT: ret
define i64 @testmsxd(double %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
%conv = sext i32 %0 to i64
ret i64 %conv
}
; CHECK-LABEL: testmswd:
; CHECK: fcvtas w0, d0
; CHECK-NEXT: ret
define i32 @testmswd(double %x) {
entry:
%0 = tail call i32 @llvm.lround.i32.f64(double %x)
ret i32 %0
}
declare i32 @llvm.lround.i32.f32(float) nounwind readnone
declare i32 @llvm.lround.i32.f64(double) nounwind readnone