forked from OSchip/llvm-project
[WebAssembly] SIMD Splats
Implement and test SIMD splat ops. Patch by Thomas Lively Differential Revision: https://reviews.llvm.org/D50741 llvm-svn: 339744
This commit is contained in:
Derek Schuff
parent
7c6baa2184
commit
4ec8bca13e
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@ -74,6 +74,34 @@ def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
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def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
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(EXTRACT_LANE_U_I16x8 V128:$vec, (i32 LaneIdx8:$idx))>;
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// splats
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def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
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def splat4 : PatFrag<(ops node:$x), (build_vector
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node:$x, node:$x, node:$x, node:$x)>;
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def splat8 : PatFrag<(ops node:$x), (build_vector
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node:$x, node:$x, node:$x, node:$x,
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node:$x, node:$x, node:$x, node:$x)>;
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def splat16 : PatFrag<(ops node:$x), (build_vector
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node:$x, node:$x, node:$x, node:$x,
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node:$x, node:$x, node:$x, node:$x,
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node:$x, node:$x, node:$x, node:$x,
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node:$x, node:$x, node:$x, node:$x)>;
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multiclass Splat<ValueType vec_t, string name, WebAssemblyRegClass reg_t,
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PatFrag splat_pat, bits<32> simdop> {
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defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
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[(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
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name#".splat\t$dst, $x", name#".splat", simdop>;
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}
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let Defs = [ARGUMENTS] in {
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defm "" : Splat<v16i8, "i8x16", I32, splat16, 3>;
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defm "" : Splat<v8i16, "i16x8", I32, splat8, 4>;
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defm "" : Splat<v4i32, "i32x4", I32, splat4, 5>;
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defm "" : Splat<v2i64, "i64x2", I64, splat2, 6>;
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defm "" : Splat<v4f32, "f32x4", F32, splat4, 7>;
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defm "" : Splat<v2f64, "f64x2", F64, splat2, 8>;
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}
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// arithmetic
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let Defs = [ARGUMENTS] in {
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let isCommutable = 1 in
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@ -10,6 +10,20 @@ target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: splat_v16i8:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.splat $push0=, $0 # encoding: [0xfd,0x03]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <16 x i8> @splat_v16i8(i8 %x) {
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%v = insertelement <16 x i8> undef, i8 %x, i32 0
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%res = shufflevector <16 x i8> %v, <16 x i8> undef,
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<16 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0,
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i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <16 x i8> %res
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}
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; CHECK-LABEL: extract_v16i8_s:
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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@ -48,6 +62,19 @@ define i8 @extract_v16i8(<16 x i8> %v) {
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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; CHECK-LABEL: splat_v8i16:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.splat $push0=, $0 # encoding: [0xfd,0x04]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <8 x i16> @splat_v8i16(i16 %x) {
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%v = insertelement <8 x i16> undef, i16 %x, i32 0
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%res = shufflevector <8 x i16> %v, <8 x i16> undef,
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<8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i16> %res
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}
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; CHECK-LABEL: extract_v8i16_s:
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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@ -86,6 +113,19 @@ define i16 @extract_v8i16(<8 x i16> %v) {
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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; CHECK-LABEL: splat_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param i32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.splat $push0=, $0 # encoding: [0xfd,0x05]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x i32> @splat_v4i32(i32 %x) {
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%v = insertelement <4 x i32> undef, i32 %x, i32 0
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%res = shufflevector <4 x i32> %v, <4 x i32> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x i32> %res
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}
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; CHECK-LABEL: extract_v4i32:
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128{{$}}
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@ -100,6 +140,19 @@ define i32 @extract_v4i32(<4 x i32> %v) {
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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; CHECK-LABEL: splat_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param i64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.splat $push0=, $0 # encoding: [0xfd,0x06]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x i64> @splat_v2i64(i64 %x) {
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%t1 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0
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%res = insertelement <2 x i64> %t1, i64 %x, i32 1
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ret <2 x i64> %res
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}
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; CHECK-LABEL: extract_v2i64:
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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@ -115,6 +168,19 @@ define i64 @extract_v2i64(<2 x i64> %v) {
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; ==============================================================================
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; 4 x f32
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; ==============================================================================
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; CHECK-LABEL: splat_v4f32:
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param f32{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.splat $push0=, $0 # encoding: [0xfd,0x07]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <4 x float> @splat_v4f32(float %x) {
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%v = insertelement <4 x float> undef, float %x, i32 0
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%res = shufflevector <4 x float> %v, <4 x float> undef,
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<4 x i32> <i32 0, i32 0, i32 0, i32 0>
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ret <4 x float> %res
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}
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; CHECK-LABEL: extract_v4f32:
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128{{$}}
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@ -129,6 +195,19 @@ define float @extract_v4f32(<4 x float> %v) {
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; ==============================================================================
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; 2 x f64
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; ==============================================================================
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; CHECK-LABEL: splat_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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; SIMD128: .param f64{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f64x2.splat $push0=, $0 # encoding: [0xfd,0x08]{{$}}
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; SIMD128: return $pop0 # encoding: [0x0f]{{$}}
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define <2 x double> @splat_v2f64(double %x) {
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%t1 = insertelement <2 x double> zeroinitializer, double %x, i3 0
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%res = insertelement <2 x double> %t1, double %x, i32 1
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ret <2 x double> %res
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}
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; CHECK-LABEL: extract_v2f64:
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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