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Cortex-R5 can issue Thumb2 integer division instructions. 

llvm-svn: 183275
This commit is contained in:
Evan Cheng 2013-06-04 22:52:09 +00:00
parent db7a52a6e7
commit 4ec309700b
3 changed files with 25 additions and 21 deletions
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3
llvm/lib/Target/ARM/ARM.td
View File

@ -177,7 +177,8 @@ def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
FeatureTrustZone]>;
def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
"Cortex-R5 ARM processors",
[FeatureSlowFPBrcc, FeatureHWDivARM,
[FeatureSlowFPBrcc,
FeatureHWDiv, FeatureHWDivARM,
FeatureHasSlowFPVMLx,
FeatureAvoidPartialCPSR,
FeatureT2XtPk]>;

23
llvm/test/CodeGen/ARM/div.ll
View File

@ -1,13 +1,14 @@
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-SWIFT
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV
define i32 @f1(i32 %a, i32 %b) {
entry:
; CHECK-ARM: f1
; CHECK-ARM: __divsi3
; CHECK-SWIFT: f1
; CHECK-SWIFT: sdiv
; CHECK-HWDIV: f1
; CHECK-HWDIV: sdiv
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -17,8 +18,8 @@ entry:
; CHECK-ARM: f2
; CHECK-ARM: __udivsi3
; CHECK-SWIFT: f2
; CHECK-SWIFT: udiv
; CHECK-HWDIV: f2
; CHECK-HWDIV: udiv
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -28,9 +29,9 @@ entry:
; CHECK-ARM: f3
; CHECK-ARM: __modsi3
; CHECK-SWIFT: f3
; CHECK-SWIFT: sdiv
; CHECK-SWIFT: mls
; CHECK-HWDIV: f3
; CHECK-HWDIV: sdiv
; CHECK-HWDIV: mls
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -40,9 +41,9 @@ entry:
; CHECK-ARM: f4
; CHECK-ARM: __umodsi3
; CHECK-SWIFT: f4
; CHECK-SWIFT: udiv
; CHECK-SWIFT: mls
; CHECK-HWDIV: f4
; CHECK-HWDIV: udiv
; CHECK-HWDIV: mls
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}

20
llvm/test/CodeGen/Thumb2/div.ll
View File

@ -3,7 +3,9 @@
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 -mattr=+thumb2 \
; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M
; RUN: llc < %s -march=thumb -mcpu=swift \
; RUN: | FileCheck %s -check-prefix=CHECK-SWIFT-T2
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
; RUN: llc < %s -march=thumb -mcpu=cortex-r5 \
; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
define i32 @f1(i32 %a, i32 %b) {
entry:
@ -11,8 +13,8 @@ entry:
; CHECK-THUMB: __divsi3
; CHECK-THUMBV7M: f1
; CHECK-THUMBV7M: sdiv
; CHECK-SWIFT-T2: f1
; CHECK-SWIFT-T2: sdiv
; CHECK-HWDIV: f1
; CHECK-HWDIV: sdiv
%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -23,8 +25,8 @@ entry:
; CHECK-THUMB: __udivsi3
; CHECK-THUMBV7M: f2
; CHECK-THUMBV7M: udiv
; CHECK-SWIFT-T2: f2
; CHECK-SWIFT-T2: udiv
; CHECK-HWDIV: f2
; CHECK-HWDIV: udiv
%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -35,8 +37,8 @@ entry:
; CHECK-THUMB: __modsi3
; CHECK-THUMBV7M: f3
; CHECK-THUMBV7M: sdiv
; CHECK-SWIFT-T2: f3
; CHECK-SWIFT-T2: sdiv
; CHECK-HWDIV: f3
; CHECK-HWDIV: sdiv
%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}
@ -47,8 +49,8 @@ entry:
; CHECK-THUMB: __umodsi3
; CHECK-THUMBV7M: f4
; CHECK-THUMBV7M: udiv
; CHECK-SWIFT-T2: f4
; CHECK-SWIFT-T2: udiv
; CHECK-HWDIV: f4
; CHECK-HWDIV: udiv
%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
ret i32 %tmp1
}