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[mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 

Differential Revision: http://reviews.llvm.org/D5211

llvm-svn: 217675
This commit is contained in:
Zoran Jovanovic 2014-09-12 13:33:33 +00:00
parent a9f47b6bae
commit 4e7ac4ad2a
4 changed files with 31 additions and 5 deletions
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9
llvm/lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -633,3 +633,12 @@ class COMPACT_BRANCH_FM_MM<bits<5> funct> {
let Inst{20-16} = rs;
let Inst{15-0} = offset;
}
class COP0_TLB_FM_MM<bits<10> op> : MMArch {
bits<32> Inst;
let Inst{31-26} = 0x0;
let Inst{25-16} = 0x0;
let Inst{15-6} = op;
let Inst{5-0} = 0x3c;
}

5
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -311,6 +311,11 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
/// Load-linked, Store-conditional
def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>;
def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>;
def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>;
def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>;
def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>;
def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
}
//===----------------------------------------------------------------------===//

10
llvm/lib/Target/Mips/MipsInstrInfo.td
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@ -1409,11 +1409,11 @@ def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
FrmOther>;
def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
FrmOther, asmstr>;
def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),

12
llvm/test/MC/Mips/micromips-control-instructions.s
View File

@ -24,6 +24,10 @@
# CHECK-EL: ei $10 # encoding: [0x0a,0x00,0x7c,0x57]
# CHECK-EL: wait # encoding: [0x00,0x00,0x7c,0x93]
# CHECK-EL: wait 17 # encoding: [0x11,0x00,0x7c,0x93]
# CHECK-EL: tlbp # encoding: [0x00,0x00,0x7c,0x03]
# CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13]
# CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23]
# CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33]
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@ -42,6 +46,10 @@
# CHECK-EB: ei $10 # encoding: [0x00,0x0a,0x57,0x7c]
# CHECK-EB: wait # encoding: [0x00,0x00,0x93,0x7c]
# CHECK-EB: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
# CHECK-EB: tlbp # encoding: [0x00,0x00,0x03,0x7c]
# CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c]
# CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c]
# CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c]
break
break 7
@ -58,3 +66,7 @@
ei $10
wait
wait 17
tlbp
tlbr
tlbwi
tlbwr