forked from OSchip/llvm-project
[AMDGPU] Split out new helper function macToMad in SIFoldOperands. NFC.
Differential Revision: https://reviews.llvm.org/D94009
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@ -129,6 +129,21 @@ char SIFoldOperands::ID = 0;
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char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
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char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
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// Map multiply-accumulate opcode to corresponding multiply-add opcode if any.
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static unsigned macToMad(unsigned Opc) {
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switch (Opc) {
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case AMDGPU::V_MAC_F32_e64:
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return AMDGPU::V_MAD_F32;
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case AMDGPU::V_MAC_F16_e64:
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return AMDGPU::V_MAD_F16;
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case AMDGPU::V_FMAC_F32_e64:
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return AMDGPU::V_FMA_F32;
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case AMDGPU::V_FMAC_F16_e64:
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return AMDGPU::V_FMA_F16_gfx9;
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}
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return AMDGPU::INSTRUCTION_LIST_END;
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}
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// Wrapper around isInlineConstant that understands special cases when
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// Wrapper around isInlineConstant that understands special cases when
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// instruction types are replaced during operand folding.
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// instruction types are replaced during operand folding.
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static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
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static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
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@ -139,31 +154,18 @@ static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
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return true;
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return true;
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unsigned Opc = UseMI.getOpcode();
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unsigned Opc = UseMI.getOpcode();
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switch (Opc) {
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unsigned NewOpc = macToMad(Opc);
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case AMDGPU::V_MAC_F32_e64:
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if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
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case AMDGPU::V_MAC_F16_e64:
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case AMDGPU::V_FMAC_F32_e64:
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case AMDGPU::V_FMAC_F16_e64: {
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// Special case for mac. Since this is replaced with mad when folded into
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// Special case for mac. Since this is replaced with mad when folded into
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// src2, we need to check the legality for the final instruction.
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// src2, we need to check the legality for the final instruction.
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
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int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
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if (static_cast<int>(OpNo) == Src2Idx) {
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if (static_cast<int>(OpNo) == Src2Idx) {
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bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
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const MCInstrDesc &MadDesc = TII->get(NewOpc);
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Opc == AMDGPU::V_FMAC_F16_e64;
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bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F32_e64;
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unsigned Opc = IsFMA ?
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(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
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(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
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const MCInstrDesc &MadDesc = TII->get(Opc);
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return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
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return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
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}
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}
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return false;
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}
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default:
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return false;
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}
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}
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return false;
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}
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}
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// TODO: Add heuristic that the frame index might not fit in the addressing mode
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// TODO: Add heuristic that the frame index might not fit in the addressing mode
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@ -346,17 +348,8 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
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if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
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// Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
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// Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
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unsigned Opc = MI->getOpcode();
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unsigned Opc = MI->getOpcode();
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if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
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unsigned NewOpc = macToMad(Opc);
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Opc == AMDGPU::V_FMAC_F32_e64 || Opc == AMDGPU::V_FMAC_F16_e64) &&
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if (NewOpc != AMDGPU::INSTRUCTION_LIST_END) {
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(int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
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bool IsFMA = Opc == AMDGPU::V_FMAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F16_e64;
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bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64 ||
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Opc == AMDGPU::V_FMAC_F32_e64;
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unsigned NewOpc = IsFMA ?
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(IsF32 ? AMDGPU::V_FMA_F32 : AMDGPU::V_FMA_F16_gfx9) :
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(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
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// Check if changing this to a v_mad_{f16, f32} instruction will allow us
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// Check if changing this to a v_mad_{f16, f32} instruction will allow us
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// to fold the operand.
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// to fold the operand.
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MI->setDesc(TII->get(NewOpc));
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MI->setDesc(TII->get(NewOpc));
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