forked from OSchip/llvm-project
[LV][VPlan] Change to implement VPlan based predication for
VPlan-native path Context: Patch Series #2 for outer loop vectorization support in LV using VPlan. (RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html). Patch series #2 checks that inner loops are still trivially lock-step among all vector elements. Non-loop branches are blindly assumed as divergent. Changes here implement VPlan based predication algorithm to compute predicates for blocks that need predication. Predicates are computed for the VPLoop region in reverse post order. A block's predicate is computed as OR of the masks of all incoming edges. The mask for an incoming edge is computed as AND of predecessor block's predicate and either predecessor's Condition bit or NOT(Condition bit) depending on whether the edge from predecessor block to the current block is true or false edge. Reviewers: fhahn, rengolin, hsaito, dcaballe Reviewed By: fhahn Patch by Satish Guggilla, thanks! Differential Revision: https://reviews.llvm.org/D53349 llvm-svn: 351990
This commit is contained in:
Hideki Saito
parent
020ce3f026
commit
4e4ecae028
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@ -7,6 +7,7 @@ add_llvm_library(LLVMVectorize
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VPlan.cpp
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VPlanHCFGBuilder.cpp
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VPlanHCFGTransforms.cpp
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VPlanPredicator.cpp
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VPlanSLP.cpp
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VPlanVerifier.cpp
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@ -22,6 +22,8 @@ using namespace llvm;
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#define LV_NAME "loop-vectorize"
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#define DEBUG_TYPE LV_NAME
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extern cl::opt<bool> EnableVPlanPredication;
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static cl::opt<bool>
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EnableIfConversion("enable-if-conversion", cl::init(true), cl::Hidden,
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cl::desc("Enable if-conversion during vectorization."));
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@ -487,7 +489,10 @@ bool LoopVectorizationLegality::canVectorizeOuterLoop() {
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// Check whether the BranchInst is a supported one. Only unconditional
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// branches, conditional branches with an outer loop invariant condition or
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// backedges are supported.
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if (Br && Br->isConditional() &&
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// FIXME: We skip these checks when VPlan predication is enabled as we
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// want to allow divergent branches. This whole check will be removed
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// once VPlan predication is on by default.
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if (!EnableVPlanPredication && Br && Br->isConditional() &&
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!TheLoop->isLoopInvariant(Br->getCondition()) &&
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!LI->isLoopHeader(Br->getSuccessor(0)) &&
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!LI->isLoopHeader(Br->getSuccessor(1))) {
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@ -58,6 +58,7 @@
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#include "VPRecipeBuilder.h"
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#include "VPlanHCFGBuilder.h"
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#include "VPlanHCFGTransforms.h"
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#include "VPlanPredicator.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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@ -255,6 +256,13 @@ cl::opt<bool> EnableVPlanNativePath(
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cl::desc("Enable VPlan-native vectorization path with "
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"support for outer loop vectorization."));
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// FIXME: Remove this switch once we have divergence analysis. Currently we
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// assume divergent non-backedge branches when this switch is true.
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cl::opt<bool> EnableVPlanPredication(
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"enable-vplan-predication", cl::init(false), cl::Hidden,
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cl::desc("Enable VPlan-native vectorization path predicator with "
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"support for outer loop vectorization."));
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// This flag enables the stress testing of the VPlan H-CFG construction in the
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// VPlan-native vectorization path. It must be used in conjuction with
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// -enable-vplan-native-path. -vplan-verify-hcfg can also be used to enable the
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@ -6896,13 +6904,22 @@ LoopVectorizationPlanner::buildVPlan(VFRange &Range) {
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VPlanHCFGBuilder HCFGBuilder(OrigLoop, LI, *Plan);
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HCFGBuilder.buildHierarchicalCFG();
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for (unsigned VF = Range.Start; VF < Range.End; VF *= 2)
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Plan->addVF(VF);
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if (EnableVPlanPredication) {
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VPlanPredicator VPP(*Plan);
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VPP.predicate();
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// Avoid running transformation to recipes until masked code generation in
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// VPlan-native path is in place.
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return Plan;
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}
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SmallPtrSet<Instruction *, 1> DeadInstructions;
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VPlanHCFGTransforms::VPInstructionsToVPRecipes(
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Plan, Legal->getInductionVars(), DeadInstructions);
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for (unsigned VF = Range.Start; VF < Range.End; VF *= 2)
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Plan->addVF(VF);
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return Plan;
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}
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@ -7119,8 +7136,8 @@ static bool processLoopInVPlanNativePath(
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VectorizationFactor VF = LVP.planInVPlanNativePath(OptForSize, UserVF);
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// If we are stress testing VPlan builds, do not attempt to generate vector
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// code.
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if (VPlanBuildStressTest)
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// code. Masked vector code generation support will follow soon.
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if (VPlanBuildStressTest || EnableVPlanPredication)
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return false;
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LVP.setBestPlan(VF.Width, 1);
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@ -560,6 +560,19 @@ void VPlanPrinter::dumpBasicBlock(const VPBasicBlock *BasicBlock) {
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bumpIndent(1);
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OS << Indent << "\"" << DOT::EscapeString(BasicBlock->getName()) << ":\\n\"";
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bumpIndent(1);
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// Dump the block predicate.
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const VPValue *Pred = BasicBlock->getPredicate();
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if (Pred) {
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OS << " +\n" << Indent << " \"BlockPredicate: ";
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if (const VPInstruction *PredI = dyn_cast<VPInstruction>(Pred)) {
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PredI->printAsOperand(OS);
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OS << " (" << DOT::EscapeString(PredI->getParent()->getName())
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<< ")\\l\"";
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} else
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Pred->printAsOperand(OS);
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}
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for (const VPRecipeBase &Recipe : *BasicBlock)
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Recipe.print(OS, Indent);
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@ -352,6 +352,9 @@ private:
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/// Successor selector, null for zero or single successor blocks.
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VPValue *CondBit = nullptr;
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/// Current block predicate - null if the block does not need a predicate.
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VPValue *Predicate = nullptr;
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/// Add \p Successor as the last successor to this block.
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void appendSuccessor(VPBlockBase *Successor) {
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assert(Successor && "Cannot add nullptr successor!");
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@ -490,6 +493,12 @@ public:
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void setCondBit(VPValue *CV) { CondBit = CV; }
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VPValue *getPredicate() { return Predicate; }
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const VPValue *getPredicate() const { return Predicate; }
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void setPredicate(VPValue *Pred) { Predicate = Pred; }
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/// Set a given VPBlockBase \p Successor as the single successor of this
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/// VPBlockBase. This VPBlockBase is not added as predecessor of \p Successor.
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/// This VPBlockBase must have no successors.
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@ -520,6 +529,15 @@ public:
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appendPredecessor(Pred);
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}
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/// Remove all the predecessor of this block.
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void clearPredecessors() { Predecessors.clear(); }
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/// Remove all the successors of this block and set to null its condition bit
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void clearSuccessors() {
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Successors.clear();
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CondBit = nullptr;
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}
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/// The method which generates the output IR that correspond to this
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/// VPBlockBase, thereby "executing" the VPlan.
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virtual void execute(struct VPTransformState *State) = 0;
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@ -1490,6 +1508,41 @@ public:
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From->removeSuccessor(To);
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To->removePredecessor(From);
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}
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/// Returns true if the edge \p FromBlock -> \p ToBlock is a back-edge.
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static bool isBackEdge(const VPBlockBase *FromBlock,
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const VPBlockBase *ToBlock, const VPLoopInfo *VPLI) {
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assert(FromBlock->getParent() == ToBlock->getParent() &&
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FromBlock->getParent() && "Must be in same region");
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const VPLoop *FromLoop = VPLI->getLoopFor(FromBlock);
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const VPLoop *ToLoop = VPLI->getLoopFor(ToBlock);
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if (!FromLoop || !ToLoop || FromLoop != ToLoop)
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return false;
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// A back-edge is a branch from the loop latch to its header.
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return ToLoop->isLoopLatch(FromBlock) && ToBlock == ToLoop->getHeader();
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}
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/// Returns true if \p Block is a loop latch
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static bool blockIsLoopLatch(const VPBlockBase *Block,
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const VPLoopInfo *VPLInfo) {
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if (const VPLoop *ParentVPL = VPLInfo->getLoopFor(Block))
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return ParentVPL->isLoopLatch(Block);
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return false;
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}
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/// Count and return the number of succesors of \p PredBlock excluding any
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/// backedges.
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static unsigned countSuccessorsNoBE(VPBlockBase *PredBlock,
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VPLoopInfo *VPLI) {
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unsigned Count = 0;
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for (VPBlockBase *SuccBlock : PredBlock->getSuccessors()) {
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if (!VPBlockUtils::isBackEdge(PredBlock, SuccBlock, VPLI))
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Count++;
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}
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return Count;
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}
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};
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class VPInterleavedAccessInfo {
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@ -0,0 +1,249 @@
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//===-- VPlanPredicator.cpp -------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the VPlanPredicator class which contains the public
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/// interfaces to predicate and linearize the VPlan region.
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///
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//===----------------------------------------------------------------------===//
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#include "VPlanPredicator.h"
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#include "VPlan.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/GraphTraits.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "VPlanPredicator"
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using namespace llvm;
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// Generate VPInstructions at the beginning of CurrBB that calculate the
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// predicate being propagated from PredBB to CurrBB depending on the edge type
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// between them. For example if:
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// i. PredBB is controlled by predicate %BP, and
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// ii. The edge PredBB->CurrBB is the false edge, controlled by the condition
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// bit value %CBV then this function will generate the following two
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// VPInstructions at the start of CurrBB:
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// %IntermediateVal = not %CBV
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// %FinalVal = and %BP %IntermediateVal
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// It returns %FinalVal.
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VPValue *VPlanPredicator::getOrCreateNotPredicate(VPBasicBlock *PredBB,
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VPBasicBlock *CurrBB) {
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VPValue *CBV = PredBB->getCondBit();
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// Set the intermediate value - this is either 'CBV', or 'not CBV'
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// depending on the edge type.
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EdgeType ET = getEdgeTypeBetween(PredBB, CurrBB);
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VPValue *IntermediateVal = nullptr;
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switch (ET) {
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case EdgeType::TRUE_EDGE:
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// CurrBB is the true successor of PredBB - nothing to do here.
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IntermediateVal = CBV;
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break;
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case EdgeType::FALSE_EDGE:
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// CurrBB is the False successor of PredBB - compute not of CBV.
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IntermediateVal = Builder.createNot(CBV);
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break;
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}
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// Now AND intermediate value with PredBB's block predicate if it has one.
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VPValue *BP = PredBB->getPredicate();
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if (BP)
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return Builder.createAnd(BP, IntermediateVal);
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else
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return IntermediateVal;
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}
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// Generate a tree of ORs for all IncomingPredicates in WorkList.
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// Note: This function destroys the original Worklist.
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//
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// P1 P2 P3 P4 P5
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// \ / \ / /
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// OR1 OR2 /
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// \ | /
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// \ +/-+
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// \ / |
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// OR3 |
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// \ |
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// OR4 <- Returns this
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// |
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//
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// The algorithm uses a worklist of predicates as its main data structure.
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// We pop a pair of values from the front (e.g. P1 and P2), generate an OR
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// (in this example OR1), and push it back. In this example the worklist
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// contains {P3, P4, P5, OR1}.
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// The process iterates until we have only one element in the Worklist (OR4).
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// The last element is the root predicate which is returned.
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VPValue *VPlanPredicator::genPredicateTree(std::list<VPValue *> &Worklist) {
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if (Worklist.empty())
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return nullptr;
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// The worklist initially contains all the leaf nodes. Initialize the tree
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// using them.
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while (Worklist.size() >= 2) {
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// Pop a pair of values from the front.
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VPValue *LHS = Worklist.front();
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Worklist.pop_front();
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VPValue *RHS = Worklist.front();
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Worklist.pop_front();
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// Create an OR of these values.
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VPValue *Or = Builder.createOr(LHS, RHS);
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// Push OR to the back of the worklist.
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Worklist.push_back(Or);
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}
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assert(Worklist.size() == 1 && "Expected 1 item in worklist");
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// The root is the last node in the worklist.
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VPValue *Root = Worklist.front();
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// This root needs to replace the existing block predicate. This is done in
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// the caller function.
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return Root;
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}
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// Return whether the edge FromBlock -> ToBlock is a TRUE_EDGE or FALSE_EDGE
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VPlanPredicator::EdgeType
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VPlanPredicator::getEdgeTypeBetween(VPBlockBase *FromBlock,
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VPBlockBase *ToBlock) {
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unsigned Count = 0;
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for (VPBlockBase *SuccBlock : FromBlock->getSuccessors()) {
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if (SuccBlock == ToBlock) {
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assert(Count < 2 && "Switch not supported currently");
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return (Count == 0) ? EdgeType::TRUE_EDGE : EdgeType::FALSE_EDGE;
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}
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Count++;
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}
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llvm_unreachable("Broken getEdgeTypeBetween");
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}
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// Generate all predicates needed for CurrBlock by going through its immediate
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// predecessor blocks.
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void VPlanPredicator::createOrPropagatePredicates(VPBlockBase *CurrBlock,
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VPRegionBlock *Region) {
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// Blocks that dominate region exit inherit the predicate from the region.
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// Return after setting the predicate.
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if (VPDomTree.dominates(CurrBlock, Region->getExit())) {
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VPValue *RegionBP = Region->getPredicate();
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CurrBlock->setPredicate(RegionBP);
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return;
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}
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// Collect all incoming predicates in a worklist.
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std::list<VPValue *> IncomingPredicates;
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// Set the builder's insertion point to the top of the current BB
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VPBasicBlock *CurrBB = cast<VPBasicBlock>(CurrBlock->getEntryBasicBlock());
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Builder.setInsertPoint(CurrBB, CurrBB->begin());
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// For each predecessor, generate the VPInstructions required for
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// computing 'BP AND (not) CBV" at the top of CurrBB.
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// Collect the outcome of this calculation for all predecessors
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// into IncomingPredicates.
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for (VPBlockBase *PredBlock : CurrBlock->getPredecessors()) {
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// Skip back-edges
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if (VPBlockUtils::isBackEdge(PredBlock, CurrBlock, VPLI))
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continue;
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VPValue *IncomingPredicate = nullptr;
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unsigned NumPredSuccsNoBE =
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VPBlockUtils::countSuccessorsNoBE(PredBlock, VPLI);
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// If there is an unconditional branch to the currBB, then we don't create
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// edge predicates. We use the predecessor's block predicate instead.
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if (NumPredSuccsNoBE == 1)
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IncomingPredicate = PredBlock->getPredicate();
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else if (NumPredSuccsNoBE == 2) {
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// Emit recipes into CurrBlock if required
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assert(isa<VPBasicBlock>(PredBlock) && "Only BBs have multiple exits");
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IncomingPredicate =
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getOrCreateNotPredicate(cast<VPBasicBlock>(PredBlock), CurrBB);
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} else
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llvm_unreachable("FIXME: switch statement ?");
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if (IncomingPredicate)
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IncomingPredicates.push_back(IncomingPredicate);
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}
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// Logically OR all incoming predicates by building the Predicate Tree.
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VPValue *Predicate = genPredicateTree(IncomingPredicates);
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// Now update the block's predicate with the new one.
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CurrBlock->setPredicate(Predicate);
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}
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// Generate all predicates needed for Region.
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void VPlanPredicator::predicateRegionRec(VPRegionBlock *Region) {
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VPBasicBlock *EntryBlock = cast<VPBasicBlock>(Region->getEntry());
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ReversePostOrderTraversal<VPBlockBase *> RPOT(EntryBlock);
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// Generate edge predicates and append them to the block predicate. RPO is
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// necessary since the predecessor blocks' block predicate needs to be set
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// before the current block's block predicate can be computed.
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for (VPBlockBase *Block : make_range(RPOT.begin(), RPOT.end())) {
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// TODO: Handle nested regions once we start generating the same.
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assert(!isa<VPRegionBlock>(Block) && "Nested region not expected");
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createOrPropagatePredicates(Block, Region);
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}
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}
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// Linearize the CFG within Region.
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// TODO: Predication and linearization need RPOT for every region.
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// This traversal is expensive. Since predication is not adding new
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// blocks, we should be able to compute RPOT once in predication and
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// reuse it here. This becomes even more important once we have nested
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// regions.
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void VPlanPredicator::linearizeRegionRec(VPRegionBlock *Region) {
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ReversePostOrderTraversal<VPBlockBase *> RPOT(Region->getEntry());
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VPBlockBase *PrevBlock = nullptr;
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for (VPBlockBase *CurrBlock : make_range(RPOT.begin(), RPOT.end())) {
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// TODO: Handle nested regions once we start generating the same.
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assert(!isa<VPRegionBlock>(CurrBlock) && "Nested region not expected");
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// Linearize control flow by adding an unconditional edge between PrevBlock
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// and CurrBlock skipping loop headers and latches to keep intact loop
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// header predecessors and loop latch successors.
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if (PrevBlock && !VPLI->isLoopHeader(CurrBlock) &&
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!VPBlockUtils::blockIsLoopLatch(PrevBlock, VPLI)) {
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LLVM_DEBUG(dbgs() << "Linearizing: " << PrevBlock->getName() << "->"
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<< CurrBlock->getName() << "\n");
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PrevBlock->clearSuccessors();
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CurrBlock->clearPredecessors();
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VPBlockUtils::connectBlocks(PrevBlock, CurrBlock);
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}
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PrevBlock = CurrBlock;
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}
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}
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// Entry point. The driver function for the predicator.
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void VPlanPredicator::predicate(void) {
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||||
// Predicate the blocks within Region.
|
||||
predicateRegionRec(cast<VPRegionBlock>(Plan.getEntry()));
|
||||
|
||||
// Linearlize the blocks with Region.
|
||||
linearizeRegionRec(cast<VPRegionBlock>(Plan.getEntry()));
|
||||
}
|
||||
|
||||
VPlanPredicator::VPlanPredicator(VPlan &Plan)
|
||||
: Plan(Plan), VPLI(&(Plan.getVPLoopInfo())) {
|
||||
// FIXME: Predicator is currently computing the dominator information for the
|
||||
// top region. Once we start storing dominator information in a VPRegionBlock,
|
||||
// we can avoid this recalculation.
|
||||
VPDomTree.recalculate(*(cast<VPRegionBlock>(Plan.getEntry())));
|
||||
}
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
//===-- VPlanPredicator.h ---------------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
///
|
||||
/// \file
|
||||
/// This file defines the VPlanPredicator class which contains the public
|
||||
/// interfaces to predicate and linearize the VPlan region.
|
||||
///
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_TRANSFORMS_VECTORIZE_VPLAN_PREDICATOR_H
|
||||
#define LLVM_TRANSFORMS_VECTORIZE_VPLAN_PREDICATOR_H
|
||||
|
||||
#include "LoopVectorizationPlanner.h"
|
||||
#include "VPlan.h"
|
||||
#include "VPlanDominatorTree.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class VPlanPredicator {
|
||||
private:
|
||||
enum class EdgeType {
|
||||
TRUE_EDGE,
|
||||
FALSE_EDGE,
|
||||
};
|
||||
|
||||
// VPlan being predicated.
|
||||
VPlan &Plan;
|
||||
|
||||
// VPLoopInfo for Plan's HCFG.
|
||||
VPLoopInfo *VPLI;
|
||||
|
||||
// Dominator tree for Plan's HCFG.
|
||||
VPDominatorTree VPDomTree;
|
||||
|
||||
// VPlan builder used to generate VPInstructions for block predicates.
|
||||
VPBuilder Builder;
|
||||
|
||||
/// Get the type of edge from \p FromBlock to \p ToBlock. Returns TRUE_EDGE if
|
||||
/// \p ToBlock is either the unconditional successor or the conditional true
|
||||
/// successor of \p FromBlock and FALSE_EDGE otherwise.
|
||||
EdgeType getEdgeTypeBetween(VPBlockBase *FromBlock, VPBlockBase *ToBlock);
|
||||
|
||||
/// Create and return VPValue corresponding to the predicate for the edge from
|
||||
/// \p PredBB to \p CurrentBlock.
|
||||
VPValue *getOrCreateNotPredicate(VPBasicBlock *PredBB, VPBasicBlock *CurrBB);
|
||||
|
||||
/// Generate and return the result of ORing all the predicate VPValues in \p
|
||||
/// Worklist.
|
||||
VPValue *genPredicateTree(std::list<VPValue *> &Worklist);
|
||||
|
||||
/// Create or propagate predicate for \p CurrBlock in region \p Region using
|
||||
/// predicate(s) of its predecessor(s)
|
||||
void createOrPropagatePredicates(VPBlockBase *CurrBlock,
|
||||
VPRegionBlock *Region);
|
||||
|
||||
/// Predicate the CFG within \p Region.
|
||||
void predicateRegionRec(VPRegionBlock *Region);
|
||||
|
||||
/// Linearize the CFG within \p Region.
|
||||
void linearizeRegionRec(VPRegionBlock *Region);
|
||||
|
||||
public:
|
||||
VPlanPredicator(VPlan &Plan);
|
||||
|
||||
/// Predicate Plan's HCFG.
|
||||
void predicate(void);
|
||||
};
|
||||
} // end namespace llvm
|
||||
#endif // LLVM_TRANSFORMS_VECTORIZE_VPLAN_PREDICATOR_H
|
||||
|
|
@ -8,6 +8,7 @@ set(LLVM_LINK_COMPONENTS
|
|||
add_llvm_unittest(VectorizeTests
|
||||
VPlanDominatorTreeTest.cpp
|
||||
VPlanLoopInfoTest.cpp
|
||||
VPlanPredicatorTest.cpp
|
||||
VPlanTest.cpp
|
||||
VPlanHCFGTest.cpp
|
||||
VPlanSlpTest.cpp
|
||||
|
|
|
|||
|
|
@ -0,0 +1,230 @@
|
|||
//===- llvm/unittests/Transforms/Vectorize/VPlanPredicatorTest.cpp -----===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "../lib/Transforms/Vectorize/VPlanPredicator.h"
|
||||
#include "VPlanTestBase.h"
|
||||
#include "gtest/gtest.h"
|
||||
|
||||
namespace llvm {
|
||||
namespace {
|
||||
|
||||
class VPlanPredicatorTest : public VPlanTestBase {};
|
||||
|
||||
TEST_F(VPlanPredicatorTest, BasicPredicatorTest) {
|
||||
const char *ModuleString =
|
||||
"@arr = common global [8 x [8 x i64]] "
|
||||
"zeroinitializer, align 16\n"
|
||||
"@arr2 = common global [8 x [8 x i64]] "
|
||||
"zeroinitializer, align 16\n"
|
||||
"@arr3 = common global [8 x [8 x i64]] "
|
||||
"zeroinitializer, align 16\n"
|
||||
"define void @f(i64 %n1) {\n"
|
||||
"entry:\n"
|
||||
" br label %for.cond1.preheader\n"
|
||||
"for.cond1.preheader: \n"
|
||||
" %i1.029 = phi i64 [ 0, %entry ], [ %inc14, %for.inc13 ]\n"
|
||||
" br label %for.body3\n"
|
||||
"for.body3: \n"
|
||||
" %i2.028 = phi i64 [ 0, %for.cond1.preheader ], [ %inc, %for.inc ]\n"
|
||||
" %arrayidx4 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* "
|
||||
"@arr, i64 0, i64 %i2.028, i64 %i1.029\n"
|
||||
" %0 = load i64, i64* %arrayidx4, align 8\n"
|
||||
" %cmp5 = icmp ugt i64 %0, 10\n"
|
||||
" br i1 %cmp5, label %if.then, label %for.inc\n"
|
||||
"if.then: \n"
|
||||
" %arrayidx7 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x i64]]* "
|
||||
"@arr2, i64 0, i64 %i2.028, i64 %i1.029\n"
|
||||
" %1 = load i64, i64* %arrayidx7, align 8\n"
|
||||
" %cmp8 = icmp ugt i64 %1, 100\n"
|
||||
" br i1 %cmp8, label %if.then9, label %for.inc\n"
|
||||
"if.then9: \n"
|
||||
" %add = add nuw nsw i64 %i2.028, %i1.029\n"
|
||||
" %arrayidx11 = getelementptr inbounds [8 x [8 x i64]], [8 x [8 x "
|
||||
"i64]]* @arr3, i64 0, i64 %i2.028, i64 %i1.029\n"
|
||||
" store i64 %add, i64* %arrayidx11, align 8\n"
|
||||
" br label %for.inc\n"
|
||||
"for.inc: \n"
|
||||
" %inc = add nuw nsw i64 %i2.028, 1\n"
|
||||
" %exitcond = icmp eq i64 %inc, 8\n"
|
||||
" br i1 %exitcond, label %for.inc13, label %for.body3\n"
|
||||
"for.inc13: \n"
|
||||
" %inc14 = add nuw nsw i64 %i1.029, 1\n"
|
||||
" %exitcond30 = icmp eq i64 %inc14, 8\n"
|
||||
" br i1 %exitcond30, label %for.end15, label %for.cond1.preheader\n"
|
||||
"for.end15: \n"
|
||||
" ret void\n"
|
||||
"}\n";
|
||||
|
||||
Module &M = parseModule(ModuleString);
|
||||
|
||||
Function *F = M.getFunction("f");
|
||||
BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
|
||||
auto Plan = buildHCFG(LoopHeader);
|
||||
|
||||
VPRegionBlock *TopRegion = cast<VPRegionBlock>(Plan->getEntry());
|
||||
VPBlockBase *PH = TopRegion->getEntry();
|
||||
VPBlockBase *H = PH->getSingleSuccessor();
|
||||
VPBlockBase *InnerLoopH = H->getSingleSuccessor();
|
||||
VPBlockBase *OuterIf = InnerLoopH->getSuccessors()[0];
|
||||
VPBlockBase *InnerLoopLatch = InnerLoopH->getSuccessors()[1];
|
||||
VPBlockBase *InnerIf = OuterIf->getSuccessors()[0];
|
||||
VPValue *CBV1 = InnerLoopH->getCondBit();
|
||||
VPValue *CBV2 = OuterIf->getCondBit();
|
||||
|
||||
// Apply predication.
|
||||
VPlanPredicator VPP(*Plan);
|
||||
VPP.predicate();
|
||||
|
||||
VPBlockBase *InnerLoopLinSucc = InnerLoopH->getSingleSuccessor();
|
||||
VPBlockBase *OuterIfLinSucc = OuterIf->getSingleSuccessor();
|
||||
VPBlockBase *InnerIfLinSucc = InnerIf->getSingleSuccessor();
|
||||
VPValue *OuterIfPred = OuterIf->getPredicate();
|
||||
VPInstruction *InnerAnd =
|
||||
cast<VPInstruction>(InnerIf->getEntryBasicBlock()->begin());
|
||||
VPValue *InnerIfPred = InnerIf->getPredicate();
|
||||
|
||||
// Test block predicates
|
||||
EXPECT_NE(nullptr, CBV1);
|
||||
EXPECT_NE(nullptr, CBV2);
|
||||
EXPECT_NE(nullptr, InnerAnd);
|
||||
EXPECT_EQ(CBV1, OuterIfPred);
|
||||
EXPECT_EQ(InnerAnd->getOpcode(), Instruction::And);
|
||||
EXPECT_EQ(InnerAnd->getOperand(0), CBV1);
|
||||
EXPECT_EQ(InnerAnd->getOperand(1), CBV2);
|
||||
EXPECT_EQ(InnerIfPred, InnerAnd);
|
||||
|
||||
// Test Linearization
|
||||
EXPECT_EQ(InnerLoopLinSucc, OuterIf);
|
||||
EXPECT_EQ(OuterIfLinSucc, InnerIf);
|
||||
EXPECT_EQ(InnerIfLinSucc, InnerLoopLatch);
|
||||
}
|
||||
|
||||
// Test generation of Not and Or during predication.
|
||||
TEST_F(VPlanPredicatorTest, PredicatorNegOrTest) {
|
||||
const char *ModuleString =
|
||||
"@arr = common global [100 x [100 x i32]] zeroinitializer, align 16\n"
|
||||
"@arr2 = common global [100 x [100 x i32]] zeroinitializer, align 16\n"
|
||||
"@arr3 = common global [100 x [100 x i32]] zeroinitializer, align 16\n"
|
||||
"define void @foo() {\n"
|
||||
"entry:\n"
|
||||
" br label %for.cond1.preheader\n"
|
||||
"for.cond1.preheader: \n"
|
||||
" %indvars.iv42 = phi i64 [ 0, %entry ], [ %indvars.iv.next43, "
|
||||
"%for.inc22 ]\n"
|
||||
" br label %for.body3\n"
|
||||
"for.body3: \n"
|
||||
" %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ "
|
||||
"%indvars.iv.next, %if.end21 ]\n"
|
||||
" %arrayidx5 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 "
|
||||
"x i32]]* @arr, i64 0, i64 %indvars.iv, i64 %indvars.iv42\n"
|
||||
" %0 = load i32, i32* %arrayidx5, align 4\n"
|
||||
" %cmp6 = icmp slt i32 %0, 100\n"
|
||||
" br i1 %cmp6, label %if.then, label %if.end21\n"
|
||||
"if.then: \n"
|
||||
" %cmp7 = icmp sgt i32 %0, 10\n"
|
||||
" br i1 %cmp7, label %if.then8, label %if.else\n"
|
||||
"if.then8: \n"
|
||||
" %add = add nsw i32 %0, 10\n"
|
||||
" %arrayidx12 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 "
|
||||
"x i32]]* @arr2, i64 0, i64 %indvars.iv, i64 %indvars.iv42\n"
|
||||
" store i32 %add, i32* %arrayidx12, align 4\n"
|
||||
" br label %if.end\n"
|
||||
"if.else: \n"
|
||||
" %sub = add nsw i32 %0, -10\n"
|
||||
" %arrayidx16 = getelementptr inbounds [100 x [100 x i32]], [100 x [100 "
|
||||
"x i32]]* @arr3, i64 0, i64 %indvars.iv, i64 %indvars.iv42\n"
|
||||
" store i32 %sub, i32* %arrayidx16, align 4\n"
|
||||
" br label %if.end\n"
|
||||
"if.end: \n"
|
||||
" store i32 222, i32* %arrayidx5, align 4\n"
|
||||
" br label %if.end21\n"
|
||||
"if.end21: \n"
|
||||
" %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1\n"
|
||||
" %exitcond = icmp eq i64 %indvars.iv.next, 100\n"
|
||||
" br i1 %exitcond, label %for.inc22, label %for.body3\n"
|
||||
"for.inc22: \n"
|
||||
" %indvars.iv.next43 = add nuw nsw i64 %indvars.iv42, 1\n"
|
||||
" %exitcond44 = icmp eq i64 %indvars.iv.next43, 100\n"
|
||||
" br i1 %exitcond44, label %for.end24, label %for.cond1.preheader\n"
|
||||
"for.end24: \n"
|
||||
" ret void\n"
|
||||
"}\n";
|
||||
|
||||
Module &M = parseModule(ModuleString);
|
||||
Function *F = M.getFunction("foo");
|
||||
BasicBlock *LoopHeader = F->getEntryBlock().getSingleSuccessor();
|
||||
auto Plan = buildHCFG(LoopHeader);
|
||||
|
||||
VPRegionBlock *TopRegion = cast<VPRegionBlock>(Plan->getEntry());
|
||||
VPBlockBase *PH = TopRegion->getEntry();
|
||||
VPBlockBase *H = PH->getSingleSuccessor();
|
||||
VPBlockBase *OuterIfCmpBlk = H->getSingleSuccessor();
|
||||
VPBlockBase *InnerIfCmpBlk = OuterIfCmpBlk->getSuccessors()[0];
|
||||
VPBlockBase *InnerIfTSucc = InnerIfCmpBlk->getSuccessors()[0];
|
||||
VPBlockBase *InnerIfFSucc = InnerIfCmpBlk->getSuccessors()[1];
|
||||
VPBlockBase *TSuccSucc = InnerIfTSucc->getSingleSuccessor();
|
||||
VPBlockBase *FSuccSucc = InnerIfFSucc->getSingleSuccessor();
|
||||
|
||||
VPValue *OuterCBV = OuterIfCmpBlk->getCondBit();
|
||||
VPValue *InnerCBV = InnerIfCmpBlk->getCondBit();
|
||||
|
||||
// Apply predication.
|
||||
VPlanPredicator VPP(*Plan);
|
||||
VPP.predicate();
|
||||
|
||||
VPInstruction *And =
|
||||
cast<VPInstruction>(InnerIfTSucc->getEntryBasicBlock()->begin());
|
||||
VPInstruction *Not =
|
||||
cast<VPInstruction>(InnerIfFSucc->getEntryBasicBlock()->begin());
|
||||
VPInstruction *NotAnd = cast<VPInstruction>(
|
||||
&*std::next(InnerIfFSucc->getEntryBasicBlock()->begin(), 1));
|
||||
VPInstruction *Or =
|
||||
cast<VPInstruction>(TSuccSucc->getEntryBasicBlock()->begin());
|
||||
|
||||
// Test block predicates
|
||||
EXPECT_NE(nullptr, OuterCBV);
|
||||
EXPECT_NE(nullptr, InnerCBV);
|
||||
EXPECT_NE(nullptr, And);
|
||||
EXPECT_NE(nullptr, Not);
|
||||
EXPECT_NE(nullptr, NotAnd);
|
||||
|
||||
EXPECT_EQ(And->getOpcode(), Instruction::And);
|
||||
EXPECT_EQ(NotAnd->getOpcode(), Instruction::And);
|
||||
EXPECT_EQ(Not->getOpcode(), VPInstruction::Not);
|
||||
|
||||
EXPECT_EQ(And->getOperand(0), OuterCBV);
|
||||
EXPECT_EQ(And->getOperand(1), InnerCBV);
|
||||
|
||||
EXPECT_EQ(Not->getOperand(0), InnerCBV);
|
||||
|
||||
EXPECT_EQ(NotAnd->getOperand(0), OuterCBV);
|
||||
EXPECT_EQ(NotAnd->getOperand(1), Not);
|
||||
|
||||
EXPECT_EQ(InnerIfTSucc->getPredicate(), And);
|
||||
EXPECT_EQ(InnerIfFSucc->getPredicate(), NotAnd);
|
||||
|
||||
EXPECT_EQ(TSuccSucc, FSuccSucc);
|
||||
EXPECT_EQ(Or->getOpcode(), Instruction::Or);
|
||||
EXPECT_EQ(TSuccSucc->getPredicate(), Or);
|
||||
|
||||
// Test operands of the Or - account for differences in predecessor block
|
||||
// ordering.
|
||||
VPInstruction *OrOp0Inst = cast<VPInstruction>(Or->getOperand(0));
|
||||
VPInstruction *OrOp1Inst = cast<VPInstruction>(Or->getOperand(1));
|
||||
|
||||
bool ValidOrOperands = false;
|
||||
if (((OrOp0Inst == And) && (OrOp1Inst == NotAnd)) ||
|
||||
((OrOp0Inst == NotAnd) && (OrOp1Inst == And)))
|
||||
ValidOrOperands = true;
|
||||
|
||||
EXPECT_TRUE(ValidOrOperands);
|
||||
}
|
||||
|
||||
} // namespace
|
||||
} // namespace llvm
|
||||
Loading…
Reference in New Issue