Add versions of OutputArgReg, AnalyzeReturn, and AnalyzeCallOperands

which do not depend on SelectionDAG.

llvm-svn: 107666

llvm/include/llvm/CodeGen/CallingConvLower.h

@@ -185,6 +185,8 @@ public:
   /// incorporating info about the result values into this state.
   void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
                      CCAssignFn Fn);
+  void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                     CCAssignFn Fn);
 
   /// CheckReturn - Analyze the return values of a function, returning
   /// true if the return can be performed without sret-demotion, and
@@ -197,6 +199,8 @@ public:
   /// incorporating info about the passed values into this state.
   void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
                            CCAssignFn Fn);
+  void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                           CCAssignFn Fn);
 
   /// AnalyzeCallOperands - Same as above except it takes vectors of types
   /// and argument flags.

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

@@ -1583,6 +1583,23 @@ namespace ISD {
              "OutputArg value type must be Simple!");
     }
   };
+
+  /// OutputArgReg - This struct carries flags and a register value for a
+  /// single outgoing (actual) argument or outgoing (from the perspective
+  /// of the caller) return value virtual register.
+  ///
+  struct OutputArgReg {
+    ArgFlagsTy Flags;
+    EVT VT;
+    unsigned Reg;
+
+    /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
+    bool IsFixed;
+
+    OutputArgReg() : IsFixed(false) {}
+    OutputArgReg(ISD::ArgFlagsTy flags, EVT vt, unsigned reg, bool isfixed)
+      : Flags(flags), VT(vt), Reg(reg), IsFixed(isfixed) {}
+  };
 }
 
 /// VTSDNode - This class is used to represent EVT's, which are used

llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp

@@ -111,6 +111,22 @@ void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
   }
 }
 
+void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                            CCAssignFn Fn) {
+  // Determine which register each value should be copied into.
+  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
+    EVT VT = Outs[i].VT;
+    ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
+    if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
+#ifndef NDEBUG
+      dbgs() << "Return operand #" << i << " has unhandled type "
+             << VT.getEVTString();
+#endif
+      llvm_unreachable(0);
+    }
+  }
+}
+
 
 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
 /// incorporating info about the passed values into this state.
@@ -130,6 +146,25 @@ void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
   }
 }
 
+/// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
+/// incorporating info about the passed values into this state.
+void
+CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArgReg> &Outs,
+                             CCAssignFn Fn) {
+  unsigned NumOps = Outs.size();
+  for (unsigned i = 0; i != NumOps; ++i) {
+    EVT ArgVT = Outs[i].VT;
+    ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
+    if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
+#ifndef NDEBUG
+      dbgs() << "Call operand #" << i << " has unhandled type "
+             << ArgVT.getEVTString();
+#endif
+      llvm_unreachable(0);
+    }
+  }
+}
+
 /// AnalyzeCallOperands - Same as above except it takes vectors of types
 /// and argument flags.
 void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,