[x86] enable machine combiner reassociations for scalar single-precision maximums

llvm-svn: 245504

llvm/lib/Target/X86/X86InstrInfo.cpp

@@ -6394,7 +6394,9 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
   // Normal min/max instructions are not commutative because of NaN and signed
   // zero semantics, but these are. Thus, there's no need to check for global
   // relaxed math; the instructions themselves have the properties we need.
+  case X86::MAXCSSrr:
   case X86::MINCSSrr:
+  case X86::VMAXCSSrr:
   case X86::VMINCSSrr:
     return true;
   case X86::ADDPDrr:

llvm/test/CodeGen/X86/machine-combiner.ll

@@ -382,3 +382,27 @@ define float @reassociate_mins_single(float %x0, float %x1, float %x2, float %x3
   ret float %sel2
 }
 
+; Verify that SSE and AVX scalar single-precision maximum ops are reassociated.
+
+define float @reassociate_maxs_single(float %x0, float %x1, float %x2, float %x3) {
+; SSE-LABEL: reassociate_maxs_single:
+; SSE:       # BB#0:
+; SSE-NEXT:    divss %xmm1, %xmm0
+; SSE-NEXT:    maxss %xmm3, %xmm2
+; SSE-NEXT:    maxss %xmm2, %xmm0
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: reassociate_maxs_single:
+; AVX:       # BB#0:
+; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmaxss %xmm3, %xmm2, %xmm1
+; AVX-NEXT:    vmaxss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    retq
+  %t0 = fdiv float %x0, %x1
+  %cmp1 = fcmp ogt float %x2, %t0
+  %sel1 = select i1 %cmp1, float %x2, float %t0
+  %cmp2 = fcmp ogt float %x3, %sel1
+  %sel2 = select i1 %cmp2, float %x3, float %sel1
+  ret float %sel2
+}
+