[ARM] Use CHECK-NEXT in CodeGen/ARM/O3-pipeline.ll. NFC.

Use CHECK-NEXT, like in other pipeline tests, so that we actually
notice when the pipeline is changed.

llvm-svn: 361810

llvm/test/CodeGen/ARM/O3-pipeline.ll

@@ -2,148 +2,148 @@
 
 ; REQUIRES: asserts
 
-; CHECK:  ModulePass Manager
-; CHECK:    Pre-ISel Intrinsic Lowering
-; CHECK:    FunctionPass Manager
-; CHECK:      Expand Atomic instructions
-; CHECK:      Simplify the CFG
-; CHECK:      Dominator Tree Construction
-; CHECK:      Basic Alias Analysis (stateless AA impl)
-; CHECK:      Module Verifier
-; CHECK:      Natural Loop Information
-; CHECK:      Canonicalize natural loops
-; CHECK:      Scalar Evolution Analysis
-; CHECK:      Loop Pass Manager
-; CHECK:        Induction Variable Users
-; CHECK:        Loop Strength Reduction
-; CHECK:      Basic Alias Analysis (stateless AA impl)
-; CHECK:      Function Alias Analysis Results
-; CHECK:      Merge contiguous icmps into a memcmp
-; CHECK:      Expand memcmp() to load/stores
-; CHECK:      Lower Garbage Collection Instructions
-; CHECK:      Shadow Stack GC Lowering
-; CHECK:      Remove unreachable blocks from the CFG
-; CHECK:      Dominator Tree Construction
-; CHECK:      Natural Loop Information
-; CHECK:      Branch Probability Analysis
-; CHECK:      Block Frequency Analysis
-; CHECK:      Constant Hoisting
-; CHECK:      Partially inline calls to library functions
-; CHECK:      Instrument function entry/exit with calls to e.g. mcount() (post inlining)
-; CHECK:      Scalarize Masked Memory Intrinsics
-; CHECK:      Expand reduction intrinsics
-; CHECK:      Dominator Tree Construction
-; CHECK:      Natural Loop Information
-; CHECK:      Scalar Evolution Analysis
-; CHECK:      Basic Alias Analysis (stateless AA impl)
-; CHECK:      Function Alias Analysis Results
-; CHECK:      Loop Pass Manager
-; CHECK:        Transform loops to use DSP intrinsics
-; CHECK:      Interleaved Access Pass
-; CHECK:      ARM IR optimizations
-; CHECK:      Dominator Tree Construction
-; CHECK:      Natural Loop Information
-; CHECK:      CodeGen Prepare
-; CHECK:    Rewrite Symbols
-; CHECK:    FunctionPass Manager
-; CHECK:      Dominator Tree Construction
-; CHECK:      Exception handling preparation
-; CHECK:      Merge internal globals
-; CHECK:      Safe Stack instrumentation pass
-; CHECK:      Insert stack protectors
-; CHECK:      Module Verifier
-; CHECK:      Dominator Tree Construction
-; CHECK:      Basic Alias Analysis (stateless AA impl)
-; CHECK:      Function Alias Analysis Results
-; CHECK:      Natural Loop Information
-; CHECK:      Branch Probability Analysis
-; CHECK:      ARM Instruction Selection
-; CHECK:      Expand ISel Pseudo-instructions
-; CHECK:      Early Tail Duplication
-; CHECK:      Optimize machine instruction PHIs
-; CHECK:      Slot index numbering
-; CHECK:      Merge disjoint stack slots
-; CHECK:      Local Stack Slot Allocation
-; CHECK:      Remove dead machine instructions
-; CHECK:      MachineDominator Tree Construction
-; CHECK:      Machine Natural Loop Construction
-; CHECK:      Early Machine Loop Invariant Code Motion
-; CHECK:      Machine Common Subexpression Elimination
-; CHECK:      MachinePostDominator Tree Construction
-; CHECK:      Machine Block Frequency Analysis
-; CHECK:      Machine code sinking
-; CHECK:      Peephole Optimizations
-; CHECK:      Remove dead machine instructions
-; CHECK:      ARM MLA / MLS expansion pass
-; CHECK:      ARM pre- register allocation load / store optimization pass
-; CHECK:      ARM A15 S->D optimizer
-; CHECK:      Detect Dead Lanes
-; CHECK:      Process Implicit Definitions
-; CHECK:      Remove unreachable machine basic blocks
-; CHECK:      Live Variable Analysis
-; CHECK:      MachineDominator Tree Construction
-; CHECK:      Machine Natural Loop Construction
-; CHECK:      Eliminate PHI nodes for register allocation
-; CHECK:      Two-Address instruction pass
-; CHECK:      Slot index numbering
-; CHECK:      Live Interval Analysis
-; CHECK:      Simple Register Coalescing
-; CHECK:      Rename Disconnected Subregister Components
-; CHECK:      Machine Instruction Scheduler
-; CHECK:      Machine Block Frequency Analysis
-; CHECK:      Debug Variable Analysis
-; CHECK:      Live Stack Slot Analysis
-; CHECK:      Virtual Register Map
-; CHECK:      Live Register Matrix
-; CHECK:      Bundle Machine CFG Edges
-; CHECK:      Spill Code Placement Analysis
-; CHECK:      Lazy Machine Block Frequency Analysis
-; CHECK:      Machine Optimization Remark Emitter
-; CHECK:      Greedy Register Allocator
-; CHECK:      Virtual Register Rewriter
-; CHECK:      Stack Slot Coloring
-; CHECK:      Machine Copy Propagation Pass
-; CHECK:      Machine Loop Invariant Code Motion
-; CHECK:      PostRA Machine Sink
-; CHECK:      Machine Block Frequency Analysis
-; CHECK:      MachinePostDominator Tree Construction
-; CHECK:      Lazy Machine Block Frequency Analysis
-; CHECK:      Machine Optimization Remark Emitter
-; CHECK:      Shrink Wrapping analysis
-; CHECK:      Prologue/Epilogue Insertion & Frame Finalization
-; CHECK:      Control Flow Optimizer
-; CHECK:      Tail Duplication
-; CHECK:      Machine Copy Propagation Pass
-; CHECK:      Post-RA pseudo instruction expansion pass
-; CHECK:      ARM load / store optimization pass
-; CHECK:      ReachingDefAnalysis
-; CHECK:      ARM Execution Domain Fix
-; CHECK:      BreakFalseDeps
-; CHECK:      ARM pseudo instruction expansion pass
-; CHECK:      Thumb2 instruction size reduce pass
-; CHECK:      MachineDominator Tree Construction
-; CHECK:      Machine Natural Loop Construction
-; CHECK:      Machine Block Frequency Analysis
-; CHECK:      If Converter
-; CHECK:      Thumb IT blocks insertion pass
-; CHECK:      MachineDominator Tree Construction
-; CHECK:      Machine Natural Loop Construction
-; CHECK:      Post RA top-down list latency scheduler
-; CHECK:      Analyze Machine Code For Garbage Collection
-; CHECK:      Machine Block Frequency Analysis
-; CHECK:      MachinePostDominator Tree Construction
-; CHECK:      Branch Probability Basic Block Placement
-; CHECK:      Thumb2 instruction size reduce pass
-; CHECK:      Unpack machine instruction bundles
-; CHECK:      optimise barriers pass
-; CHECK:      ARM constant island placement and branch shortening pass
-; CHECK:      Contiguously Lay Out Funclets
-; CHECK:      StackMap Liveness Analysis
-; CHECK:      Live DEBUG_VALUE analysis
-; CHECK:      Insert fentry calls
-; CHECK:      Insert XRay ops
-; CHECK:      Implement the 'patchable-function' attribute
-; CHECK:      Lazy Machine Block Frequency Analysis
-; CHECK:      Machine Optimization Remark Emitter
-; CHECK:      ARM Assembly Printer
-; CHECK:      Free MachineFunction
+; CHECK:       ModulePass Manager
+; CHECK-NEXT:    Pre-ISel Intrinsic Lowering
+; CHECK-NEXT:    FunctionPass Manager
+; CHECK-NEXT:      Expand Atomic instructions
+; CHECK-NEXT:      Simplify the CFG
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Module Verifier
+; CHECK-NEXT:      Natural Loop Information
+; CHECK-NEXT:      Canonicalize natural loops
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Loop Pass Manager
+; CHECK-NEXT:        Induction Variable Users
+; CHECK-NEXT:        Loop Strength Reduction
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Function Alias Analysis Results
+; CHECK-NEXT:      Merge contiguous icmps into a memcmp
+; CHECK-NEXT:      Expand memcmp() to load/stores
+; CHECK-NEXT:      Lower Garbage Collection Instructions
+; CHECK-NEXT:      Shadow Stack GC Lowering
+; CHECK-NEXT:      Remove unreachable blocks from the CFG
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Natural Loop Information
+; CHECK-NEXT:      Branch Probability Analysis
+; CHECK-NEXT:      Block Frequency Analysis
+; CHECK-NEXT:      Constant Hoisting
+; CHECK-NEXT:      Partially inline calls to library functions
+; CHECK-NEXT:      Instrument function entry/exit with calls to e.g. mcount() (post inlining)
+; CHECK-NEXT:      Scalarize Masked Memory Intrinsics
+; CHECK-NEXT:      Expand reduction intrinsics
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Natural Loop Information
+; CHECK-NEXT:      Scalar Evolution Analysis
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Function Alias Analysis Results
+; CHECK-NEXT:      Loop Pass Manager
+; CHECK-NEXT:        Transform loops to use DSP intrinsics
+; CHECK-NEXT:      Interleaved Access Pass
+; CHECK-NEXT:      ARM IR optimizations
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Natural Loop Information
+; CHECK-NEXT:      CodeGen Prepare
+; CHECK-NEXT:    Rewrite Symbols
+; CHECK-NEXT:    FunctionPass Manager
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Exception handling preparation
+; CHECK-NEXT:      Merge internal globals
+; CHECK-NEXT:      Safe Stack instrumentation pass
+; CHECK-NEXT:      Insert stack protectors
+; CHECK-NEXT:      Module Verifier
+; CHECK-NEXT:      Dominator Tree Construction
+; CHECK-NEXT:      Basic Alias Analysis (stateless AA impl)
+; CHECK-NEXT:      Function Alias Analysis Results
+; CHECK-NEXT:      Natural Loop Information
+; CHECK-NEXT:      Branch Probability Analysis
+; CHECK-NEXT:      ARM Instruction Selection
+; CHECK-NEXT:      Expand ISel Pseudo-instructions
+; CHECK-NEXT:      Early Tail Duplication
+; CHECK-NEXT:      Optimize machine instruction PHIs
+; CHECK-NEXT:      Slot index numbering
+; CHECK-NEXT:      Merge disjoint stack slots
+; CHECK-NEXT:      Local Stack Slot Allocation
+; CHECK-NEXT:      Remove dead machine instructions
+; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Early Machine Loop Invariant Code Motion
+; CHECK-NEXT:      Machine Common Subexpression Elimination
+; CHECK-NEXT:      MachinePostDominator Tree Construction
+; CHECK-NEXT:      Machine Block Frequency Analysis
+; CHECK-NEXT:      Machine code sinking
+; CHECK-NEXT:      Peephole Optimizations
+; CHECK-NEXT:      Remove dead machine instructions
+; CHECK-NEXT:      ARM MLA / MLS expansion pass
+; CHECK-NEXT:      ARM pre- register allocation load / store optimization pass
+; CHECK-NEXT:      ARM A15 S->D optimizer
+; CHECK-NEXT:      Detect Dead Lanes
+; CHECK-NEXT:      Process Implicit Definitions
+; CHECK-NEXT:      Remove unreachable machine basic blocks
+; CHECK-NEXT:      Live Variable Analysis
+; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Eliminate PHI nodes for register allocation
+; CHECK-NEXT:      Two-Address instruction pass
+; CHECK-NEXT:      Slot index numbering
+; CHECK-NEXT:      Live Interval Analysis
+; CHECK-NEXT:      Simple Register Coalescing
+; CHECK-NEXT:      Rename Disconnected Subregister Components
+; CHECK-NEXT:      Machine Instruction Scheduler
+; CHECK-NEXT:      Machine Block Frequency Analysis
+; CHECK-NEXT:      Debug Variable Analysis
+; CHECK-NEXT:      Live Stack Slot Analysis
+; CHECK-NEXT:      Virtual Register Map
+; CHECK-NEXT:      Live Register Matrix
+; CHECK-NEXT:      Bundle Machine CFG Edges
+; CHECK-NEXT:      Spill Code Placement Analysis
+; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
+; CHECK-NEXT:      Machine Optimization Remark Emitter
+; CHECK-NEXT:      Greedy Register Allocator
+; CHECK-NEXT:      Virtual Register Rewriter
+; CHECK-NEXT:      Stack Slot Coloring
+; CHECK-NEXT:      Machine Copy Propagation Pass
+; CHECK-NEXT:      Machine Loop Invariant Code Motion
+; CHECK-NEXT:      PostRA Machine Sink
+; CHECK-NEXT:      Machine Block Frequency Analysis
+; CHECK-NEXT:      MachinePostDominator Tree Construction
+; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
+; CHECK-NEXT:      Machine Optimization Remark Emitter
+; CHECK-NEXT:      Shrink Wrapping analysis
+; CHECK-NEXT:      Prologue/Epilogue Insertion & Frame Finalization
+; CHECK-NEXT:      Control Flow Optimizer
+; CHECK-NEXT:      Tail Duplication
+; CHECK-NEXT:      Machine Copy Propagation Pass
+; CHECK-NEXT:      Post-RA pseudo instruction expansion pass
+; CHECK-NEXT:      ARM load / store optimization pass
+; CHECK-NEXT:      ReachingDefAnalysis
+; CHECK-NEXT:      ARM Execution Domain Fix
+; CHECK-NEXT:      BreakFalseDeps
+; CHECK-NEXT:      ARM pseudo instruction expansion pass
+; CHECK-NEXT:      Thumb2 instruction size reduce pass
+; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Machine Block Frequency Analysis
+; CHECK-NEXT:      If Converter
+; CHECK-NEXT:      Thumb IT blocks insertion pass
+; CHECK-NEXT:      MachineDominator Tree Construction
+; CHECK-NEXT:      Machine Natural Loop Construction
+; CHECK-NEXT:      Post RA top-down list latency scheduler
+; CHECK-NEXT:      Analyze Machine Code For Garbage Collection
+; CHECK-NEXT:      Machine Block Frequency Analysis
+; CHECK-NEXT:      MachinePostDominator Tree Construction
+; CHECK-NEXT:      Branch Probability Basic Block Placement
+; CHECK-NEXT:      Thumb2 instruction size reduce pass
+; CHECK-NEXT:      Unpack machine instruction bundles
+; CHECK-NEXT:      optimise barriers pass
+; CHECK-NEXT:      ARM constant island placement and branch shortening pass
+; CHECK-NEXT:      Contiguously Lay Out Funclets
+; CHECK-NEXT:      StackMap Liveness Analysis
+; CHECK-NEXT:      Live DEBUG_VALUE analysis
+; CHECK-NEXT:      Insert fentry calls
+; CHECK-NEXT:      Insert XRay ops
+; CHECK-NEXT:      Implement the 'patchable-function' attribute
+; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
+; CHECK-NEXT:      Machine Optimization Remark Emitter
+; CHECK-NEXT:      ARM Assembly Printer
+; CHECK-NEXT:      Free MachineFunction