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[Hexagon] Calling conventions for floating point vectors 

They are the same as for the other HVX vectors, but types need to be
listed explicitly. Also, add a detailed codegen testcase.

Co-authored-by: Abhikrant Sharma <quic_abhikran@quicinc.com>
This commit is contained in:
Krzysztof Parzyszek 2021-12-29 08:46:26 -08:00
parent ee3f557a9c
commit 4df2aba294
5 changed files with 1556 additions and 13 deletions
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12
llvm/lib/Target/Hexagon/HexagonCallingConv.td
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@ -126,16 +126,16 @@ def CC_Hexagon_HVX: CallingConv<[
// HVX 128-byte mode
CCIfHvx128<
CCIfType<[v32i32,v64i16,v128i8],
CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
CCIfHvx128<
CCIfType<[v64i32,v128i16,v256i8],
CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16],
CCAssignToReg<[W0,W1,W2,W3,W4,W5,W6,W7]>>>,
CCIfHvx128<
CCIfType<[v32i32,v64i16,v128i8],
CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
CCAssignToStack<128,128>>>,
CCIfHvx128<
CCIfType<[v64i32,v128i16,v256i8],
CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16],
CCAssignToStack<256,128>>>,
CCDelegateTo<CC_Hexagon>
@ -152,10 +152,10 @@ def RetCC_Hexagon_HVX: CallingConv<[
// HVX 128-byte mode
CCIfHvx128<
CCIfType<[v32i32,v64i16,v128i8],
CCIfType<[v32i32,v64i16,v128i8,v32f32,v64f16],
CCAssignToReg<[V0]>>>,
CCIfHvx128<
CCIfType<[v64i32,v128i16,v256i8],
CCIfType<[v64i32,v128i16,v256i8,v64f32,v128f16],
CCAssignToReg<[W0]>>>,
CCDelegateTo<RetCC_Hexagon>

4
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -59,6 +59,7 @@ HexagonTargetLowering::initializeHVXLowering() {
addRegisterClass(MVT::v32f32, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v64f16, &Hexagon::HvxVRRegClass);
addRegisterClass(MVT::v64f32, &Hexagon::HvxWRRegClass);
addRegisterClass(MVT::v128f16, &Hexagon::HvxWRRegClass);
}
}
@ -104,6 +105,9 @@ HexagonTargetLowering::initializeHVXLowering() {
// independent) handling of it would convert it to a load, which is
// not always the optimal choice.
setOperationAction(ISD::BUILD_VECTOR, MVT::v64f32, Custom);
// Make concat-vectors custom to handle concats of more than 2 vectors.
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128f16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64f32, Custom);
}
for (MVT T : LegalV) {

19
llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
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@ -265,9 +265,7 @@ let Predicates = [UseHVX] in {
// These should be preferred over a vsplat of 0.
def: Pat<(VecI8 vzero), (V6_vd0)>;
def: Pat<(VecI16 vzero), (V6_vd0)>;
def: Pat<(VecF16 vzero), (V6_vd0)>;
def: Pat<(VecI32 vzero), (V6_vd0)>;
def: Pat<(VecF32 vzero), (V6_vd0)>;
def: Pat<(VecPI8 vzero), (PS_vdd0)>;
def: Pat<(VecPI16 vzero), (PS_vdd0)>;
def: Pat<(VecPI32 vzero), (PS_vdd0)>;
@ -303,7 +301,22 @@ let Predicates = [UseHVX] in {
(V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
}
let Predicates = [UseHVXFloatingPoint] in {
let Predicates = [UseHVX, UseHVXFloatingPoint] in {
let AddedComplexity = 100 in {
def: Pat<(VecF16 vzero), (V6_vd0)>;
def: Pat<(VecF32 vzero), (V6_vd0)>;
def: Pat<(VecPF16 vzero), (PS_vdd0)>;
def: Pat<(VecPF32 vzero), (PS_vdd0)>;
def: Pat<(concat_vectors (VecF16 vzero), (VecF16 vzero)), (PS_vdd0)>;
def: Pat<(concat_vectors (VecF32 vzero), (VecF32 vzero)), (PS_vdd0)>;
}
def: Pat<(VecPF16 (concat_vectors HVF16:$Vs, HVF16:$Vt)),
(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
def: Pat<(VecPF32 (concat_vectors HVF32:$Vs, HVF32:$Vt)),
(Combinev HvxVR:$Vt, HvxVR:$Vs)>;
def: Pat<(HexagonVINSERTW0 HVF16:$Vu, I32:$Rt),
(V6_vinsertwr HvxVR:$Vu, I32:$Rt)>;
def: Pat<(HexagonVINSERTW0 HVF32:$Vu, I32:$Rt),

1528
llvm/test/CodeGen/Hexagon/autohvx/calling-conv.ll Normal file
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File diff suppressed because it is too large Load Diff

6
llvm/test/CodeGen/Hexagon/autohvx/splat.ll
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@ -402,9 +402,8 @@ define <64 x half> @f24(i16 %a0) #2 {
; CHECK-LABEL: f24:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0.h = vsplat(r1)
; CHECK-NEXT: v0.h = vsplat(r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: vmem(r0+#0) = v0.new
; CHECK-NEXT: }
%v0 = bitcast i16 %a0 to half
%v1 = insertelement <64 x half> undef, half %v0, i32 0
@ -417,9 +416,8 @@ define <32 x float> @f25(float %a0) #2 {
; CHECK-LABEL: f25:
; CHECK: // %bb.0:
; CHECK-NEXT: {
; CHECK-NEXT: v0 = vsplat(r1)
; CHECK-NEXT: v0 = vsplat(r0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: vmem(r0+#0) = v0.new
; CHECK-NEXT: }
%v0 = insertelement <32 x float> undef, float %a0, i32 0
%v1 = shufflevector <32 x float> %v0, <32 x float> undef, <32 x i32> zeroinitializer