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Fix an abort in instcombine when folding creates a vector rem instruction. 

llvm-svn: 43743
This commit is contained in:
Dan Gohman 2007-11-05 23:16:33 +00:00
parent fa0df55bdd
commit 4decbc5002
2 changed files with 18 additions and 5 deletions
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14
llvm/lib/Transforms/Scalar/InstructionCombining.cpp
View File

@ -2622,6 +2622,7 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) {
if (I.getType()->isInteger()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
// X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set
return BinaryOperator::createUDiv(Op0, Op1, I.getName());
}
}
@ -2811,6 +2812,7 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
// Handle the integer rem common cases
if (Instruction *common = commonIRemTransforms(I))
return common;
@ -2823,12 +2825,14 @@ Instruction *InstCombiner::visitSRem(BinaryOperator &I) {
return &I;
}
// If the top bits of both operands are zero (i.e. we can prove they are
// If the sign bits of both operands are zero (i.e. we can prove they are
// unsigned inputs), turn this into a urem.
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set
return BinaryOperator::createURem(Op0, Op1, I.getName());
if (I.getType()->isInteger()) {
APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits()));
if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
// X srem Y -> X urem Y, iff X and Y don't have sign bit set
return BinaryOperator::createURem(Op0, Op1, I.getName());
}
}
return 0;

9
llvm/test/Transforms/InstCombine/vector-srem.ll Normal file
View File

@ -0,0 +1,9 @@
; RUN: llvm-as < %s | opt -instcombine | llvm-dis | grep {srem <4 x i32>}
define <4 x i32> @foo(<4 x i32> %t, <4 x i32> %u)
{
%k = sdiv <4 x i32> %t, %u
%l = mul <4 x i32> %k, %u
%m = sub <4 x i32> %t, %l
ret <4 x i32> %m
}