forked from OSchip/llvm-project
[SLPVectorizer][X86] Regenerate reduction tests and add PR37731 test
Cleanup check prefixes llvm-svn: 346964
This commit is contained in:
Simon Pilgrim
parent
8329028b49
commit
4dd692ec2a
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@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug < %s 2>&1 | FileCheck %s
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck --check-prefix=SSE2 %s
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX
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; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,SSE
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; REQUIRES: asserts
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; int test_add(unsigned int *p) {
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@ -11,9 +11,9 @@
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; }
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; Vector cost is 5, Scalar cost is 7
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; CHECK: Adding cost -2 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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; AVX: Adding cost -2 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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; Vector cost is 11, Scalar cost is 7
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; SSE2: Adding cost 3 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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; SSE: Adding cost 3 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
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define i32 @test_add(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_add(
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; CHECK-NEXT: entry:
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@ -42,33 +42,6 @@ define i32 @test_add(i32* nocapture readonly %p) {
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; CHECK-NEXT: [[MUL_714:%.*]] = add i32 undef, [[MUL_613]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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; SSE2-LABEL: @test_add(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE2-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
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; SSE2-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = add i32 undef, undef
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; SSE2-NEXT: [[MUL_29:%.*]] = add i32 undef, [[MUL_18]]
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; SSE2-NEXT: [[MUL_310:%.*]] = add i32 undef, [[MUL_29]]
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; SSE2-NEXT: [[MUL_411:%.*]] = add i32 undef, [[MUL_310]]
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; SSE2-NEXT: [[MUL_512:%.*]] = add i32 undef, [[MUL_411]]
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; SSE2-NEXT: [[MUL_613:%.*]] = add i32 undef, [[MUL_512]]
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; SSE2-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[TMP1]], [[RDX_SHUF]]
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; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX2:%.*]] = add <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX4:%.*]] = add <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
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; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
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; SSE2-NEXT: [[MUL_714:%.*]] = add i32 undef, [[MUL_613]]
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; SSE2-NEXT: ret i32 [[TMP2]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
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@ -129,32 +102,6 @@ define i32 @test_mul(i32* nocapture readonly %p) {
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; CHECK-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]]
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; CHECK-NEXT: ret i32 [[MUL_714]]
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;
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; SSE2-LABEL: @test_mul(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; SSE2-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = mul i32 [[TMP1]], [[TMP0]]
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; SSE2-NEXT: [[MUL_29:%.*]] = mul i32 [[TMP2]], [[MUL_18]]
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; SSE2-NEXT: [[MUL_310:%.*]] = mul i32 [[TMP3]], [[MUL_29]]
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; SSE2-NEXT: [[MUL_411:%.*]] = mul i32 [[TMP4]], [[MUL_310]]
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; SSE2-NEXT: [[MUL_512:%.*]] = mul i32 [[TMP5]], [[MUL_411]]
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE2-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; SSE2-NEXT: [[MUL_613:%.*]] = mul i32 [[TMP6]], [[MUL_512]]
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; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE2-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; SSE2-NEXT: [[MUL_714:%.*]] = mul i32 [[TMP7]], [[MUL_613]]
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; SSE2-NEXT: ret i32 [[MUL_714]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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%arrayidx.1 = getelementptr inbounds i32, i32* %p, i64 1
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@ -189,58 +136,58 @@ entry:
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; }
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define i32 @test_and(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_and(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[MUL_18:%.*]] = and i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[MUL_29:%.*]] = and i32 [[TMP2]], [[MUL_18]]
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[MUL_310:%.*]] = and i32 [[TMP3]], [[MUL_29]]
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; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; CHECK-NEXT: [[MUL_411:%.*]] = and i32 [[TMP4]], [[MUL_310]]
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; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; CHECK-NEXT: [[MUL_512:%.*]] = and i32 [[TMP5]], [[MUL_411]]
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; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; CHECK-NEXT: [[MUL_613:%.*]] = and i32 [[TMP6]], [[MUL_512]]
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; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; CHECK-NEXT: [[MUL_714:%.*]] = and i32 [[TMP7]], [[MUL_613]]
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; CHECK-NEXT: ret i32 [[MUL_714]]
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; AVX-LABEL: @test_and(
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; AVX-NEXT: entry:
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; AVX-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; AVX-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; AVX-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; AVX-NEXT: [[MUL_18:%.*]] = and i32 [[TMP1]], [[TMP0]]
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; AVX-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; AVX-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; AVX-NEXT: [[MUL_29:%.*]] = and i32 [[TMP2]], [[MUL_18]]
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; AVX-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; AVX-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; AVX-NEXT: [[MUL_310:%.*]] = and i32 [[TMP3]], [[MUL_29]]
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; AVX-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; AVX-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; AVX-NEXT: [[MUL_411:%.*]] = and i32 [[TMP4]], [[MUL_310]]
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; AVX-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; AVX-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
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; AVX-NEXT: [[MUL_512:%.*]] = and i32 [[TMP5]], [[MUL_411]]
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; AVX-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; AVX-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
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; AVX-NEXT: [[MUL_613:%.*]] = and i32 [[TMP6]], [[MUL_512]]
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; AVX-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; AVX-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
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; AVX-NEXT: [[MUL_714:%.*]] = and i32 [[TMP7]], [[MUL_613]]
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; AVX-NEXT: ret i32 [[MUL_714]]
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;
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; SSE2-LABEL: @test_and(
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; SSE2-NEXT: entry:
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; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE2-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
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; SSE2-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
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; SSE2-NEXT: [[MUL_18:%.*]] = and i32 undef, undef
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; SSE2-NEXT: [[MUL_29:%.*]] = and i32 undef, [[MUL_18]]
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; SSE2-NEXT: [[MUL_310:%.*]] = and i32 undef, [[MUL_29]]
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; SSE2-NEXT: [[MUL_411:%.*]] = and i32 undef, [[MUL_310]]
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; SSE2-NEXT: [[MUL_512:%.*]] = and i32 undef, [[MUL_411]]
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; SSE2-NEXT: [[MUL_613:%.*]] = and i32 undef, [[MUL_512]]
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; SSE2-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX:%.*]] = and <8 x i32> [[TMP1]], [[RDX_SHUF]]
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; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX2:%.*]] = and <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE2-NEXT: [[BIN_RDX4:%.*]] = and <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
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; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
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; SSE2-NEXT: [[MUL_714:%.*]] = and i32 undef, [[MUL_613]]
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; SSE2-NEXT: ret i32 [[TMP2]]
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; SSE-LABEL: @test_and(
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; SSE-NEXT: entry:
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; SSE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
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; SSE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; SSE-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; SSE-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; SSE-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
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; SSE-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
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; SSE-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
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; SSE-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
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; SSE-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
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; SSE-NEXT: [[MUL_18:%.*]] = and i32 undef, undef
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; SSE-NEXT: [[MUL_29:%.*]] = and i32 undef, [[MUL_18]]
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; SSE-NEXT: [[MUL_310:%.*]] = and i32 undef, [[MUL_29]]
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; SSE-NEXT: [[MUL_411:%.*]] = and i32 undef, [[MUL_310]]
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; SSE-NEXT: [[MUL_512:%.*]] = and i32 undef, [[MUL_411]]
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; SSE-NEXT: [[MUL_613:%.*]] = and i32 undef, [[MUL_512]]
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; SSE-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE-NEXT: [[BIN_RDX:%.*]] = and <8 x i32> [[TMP1]], [[RDX_SHUF]]
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; SSE-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE-NEXT: [[BIN_RDX2:%.*]] = and <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
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; SSE-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; SSE-NEXT: [[BIN_RDX4:%.*]] = and <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
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; SSE-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
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; SSE-NEXT: [[MUL_714:%.*]] = and i32 undef, [[MUL_613]]
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; SSE-NEXT: ret i32 [[TMP2]]
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;
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entry:
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%0 = load i32, i32* %p, align 4
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@ -276,58 +223,58 @@ entry:
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; }
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define i32 @test_or(i32* nocapture readonly %p) {
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; CHECK-LABEL: @test_or(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[MUL_18:%.*]] = or i32 [[TMP1]], [[TMP0]]
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[MUL_29:%.*]] = or i32 [[TMP2]], [[MUL_18]]
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[MUL_310:%.*]] = or i32 [[TMP3]], [[MUL_29]]
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; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
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; CHECK-NEXT: [[MUL_411:%.*]] = or i32 [[TMP4]], [[MUL_310]]
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; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; CHECK-NEXT: [[MUL_512:%.*]] = or i32 [[TMP5]], [[MUL_411]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; CHECK-NEXT: [[MUL_613:%.*]] = or i32 [[TMP6]], [[MUL_512]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; CHECK-NEXT: [[MUL_714:%.*]] = or i32 [[TMP7]], [[MUL_613]]
|
||||
; CHECK-NEXT: ret i32 [[MUL_714]]
|
||||
; AVX-LABEL: @test_or(
|
||||
; AVX-NEXT: entry:
|
||||
; AVX-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
|
||||
; AVX-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
|
||||
; AVX-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
|
||||
; AVX-NEXT: [[MUL_18:%.*]] = or i32 [[TMP1]], [[TMP0]]
|
||||
; AVX-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; AVX-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
|
||||
; AVX-NEXT: [[MUL_29:%.*]] = or i32 [[TMP2]], [[MUL_18]]
|
||||
; AVX-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; AVX-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
|
||||
; AVX-NEXT: [[MUL_310:%.*]] = or i32 [[TMP3]], [[MUL_29]]
|
||||
; AVX-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; AVX-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
|
||||
; AVX-NEXT: [[MUL_411:%.*]] = or i32 [[TMP4]], [[MUL_310]]
|
||||
; AVX-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; AVX-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; AVX-NEXT: [[MUL_512:%.*]] = or i32 [[TMP5]], [[MUL_411]]
|
||||
; AVX-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; AVX-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; AVX-NEXT: [[MUL_613:%.*]] = or i32 [[TMP6]], [[MUL_512]]
|
||||
; AVX-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; AVX-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; AVX-NEXT: [[MUL_714:%.*]] = or i32 [[TMP7]], [[MUL_613]]
|
||||
; AVX-NEXT: ret i32 [[MUL_714]]
|
||||
;
|
||||
; SSE2-LABEL: @test_or(
|
||||
; SSE2-NEXT: entry:
|
||||
; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
|
||||
; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE2-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
|
||||
; SSE2-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
|
||||
; SSE2-NEXT: [[MUL_18:%.*]] = or i32 undef, undef
|
||||
; SSE2-NEXT: [[MUL_29:%.*]] = or i32 undef, [[MUL_18]]
|
||||
; SSE2-NEXT: [[MUL_310:%.*]] = or i32 undef, [[MUL_29]]
|
||||
; SSE2-NEXT: [[MUL_411:%.*]] = or i32 undef, [[MUL_310]]
|
||||
; SSE2-NEXT: [[MUL_512:%.*]] = or i32 undef, [[MUL_411]]
|
||||
; SSE2-NEXT: [[MUL_613:%.*]] = or i32 undef, [[MUL_512]]
|
||||
; SSE2-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX:%.*]] = or <8 x i32> [[TMP1]], [[RDX_SHUF]]
|
||||
; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX2:%.*]] = or <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
|
||||
; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX4:%.*]] = or <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
|
||||
; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
|
||||
; SSE2-NEXT: [[MUL_714:%.*]] = or i32 undef, [[MUL_613]]
|
||||
; SSE2-NEXT: ret i32 [[TMP2]]
|
||||
; SSE-LABEL: @test_or(
|
||||
; SSE-NEXT: entry:
|
||||
; SSE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
|
||||
; SSE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; SSE-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; SSE-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; SSE-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; SSE-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
|
||||
; SSE-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
|
||||
; SSE-NEXT: [[MUL_18:%.*]] = or i32 undef, undef
|
||||
; SSE-NEXT: [[MUL_29:%.*]] = or i32 undef, [[MUL_18]]
|
||||
; SSE-NEXT: [[MUL_310:%.*]] = or i32 undef, [[MUL_29]]
|
||||
; SSE-NEXT: [[MUL_411:%.*]] = or i32 undef, [[MUL_310]]
|
||||
; SSE-NEXT: [[MUL_512:%.*]] = or i32 undef, [[MUL_411]]
|
||||
; SSE-NEXT: [[MUL_613:%.*]] = or i32 undef, [[MUL_512]]
|
||||
; SSE-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX:%.*]] = or <8 x i32> [[TMP1]], [[RDX_SHUF]]
|
||||
; SSE-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX2:%.*]] = or <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
|
||||
; SSE-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX4:%.*]] = or <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
|
||||
; SSE-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
|
||||
; SSE-NEXT: [[MUL_714:%.*]] = or i32 undef, [[MUL_613]]
|
||||
; SSE-NEXT: ret i32 [[TMP2]]
|
||||
;
|
||||
entry:
|
||||
%0 = load i32, i32* %p, align 4
|
||||
|
|
@ -363,58 +310,58 @@ entry:
|
|||
; }
|
||||
|
||||
define i32 @test_xor(i32* nocapture readonly %p) {
|
||||
; CHECK-LABEL: @test_xor(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
|
||||
; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
|
||||
; CHECK-NEXT: [[MUL_18:%.*]] = xor i32 [[TMP1]], [[TMP0]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
|
||||
; CHECK-NEXT: [[MUL_29:%.*]] = xor i32 [[TMP2]], [[MUL_18]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
|
||||
; CHECK-NEXT: [[MUL_310:%.*]] = xor i32 [[TMP3]], [[MUL_29]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
|
||||
; CHECK-NEXT: [[MUL_411:%.*]] = xor i32 [[TMP4]], [[MUL_310]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; CHECK-NEXT: [[MUL_512:%.*]] = xor i32 [[TMP5]], [[MUL_411]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; CHECK-NEXT: [[MUL_613:%.*]] = xor i32 [[TMP6]], [[MUL_512]]
|
||||
; CHECK-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; CHECK-NEXT: [[MUL_714:%.*]] = xor i32 [[TMP7]], [[MUL_613]]
|
||||
; CHECK-NEXT: ret i32 [[MUL_714]]
|
||||
; AVX-LABEL: @test_xor(
|
||||
; AVX-NEXT: entry:
|
||||
; AVX-NEXT: [[TMP0:%.*]] = load i32, i32* [[P:%.*]], align 4
|
||||
; AVX-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 1
|
||||
; AVX-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
|
||||
; AVX-NEXT: [[MUL_18:%.*]] = xor i32 [[TMP1]], [[TMP0]]
|
||||
; AVX-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; AVX-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
|
||||
; AVX-NEXT: [[MUL_29:%.*]] = xor i32 [[TMP2]], [[MUL_18]]
|
||||
; AVX-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; AVX-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
|
||||
; AVX-NEXT: [[MUL_310:%.*]] = xor i32 [[TMP3]], [[MUL_29]]
|
||||
; AVX-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; AVX-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX_4]], align 4
|
||||
; AVX-NEXT: [[MUL_411:%.*]] = xor i32 [[TMP4]], [[MUL_310]]
|
||||
; AVX-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; AVX-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX_5]], align 4
|
||||
; AVX-NEXT: [[MUL_512:%.*]] = xor i32 [[TMP5]], [[MUL_411]]
|
||||
; AVX-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; AVX-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX_6]], align 4
|
||||
; AVX-NEXT: [[MUL_613:%.*]] = xor i32 [[TMP6]], [[MUL_512]]
|
||||
; AVX-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; AVX-NEXT: [[TMP7:%.*]] = load i32, i32* [[ARRAYIDX_7]], align 4
|
||||
; AVX-NEXT: [[MUL_714:%.*]] = xor i32 [[TMP7]], [[MUL_613]]
|
||||
; AVX-NEXT: ret i32 [[MUL_714]]
|
||||
;
|
||||
; SSE2-LABEL: @test_xor(
|
||||
; SSE2-NEXT: entry:
|
||||
; SSE2-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
|
||||
; SSE2-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; SSE2-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; SSE2-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; SSE2-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; SSE2-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE2-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE2-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
|
||||
; SSE2-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
|
||||
; SSE2-NEXT: [[MUL_18:%.*]] = xor i32 undef, undef
|
||||
; SSE2-NEXT: [[MUL_29:%.*]] = xor i32 undef, [[MUL_18]]
|
||||
; SSE2-NEXT: [[MUL_310:%.*]] = xor i32 undef, [[MUL_29]]
|
||||
; SSE2-NEXT: [[MUL_411:%.*]] = xor i32 undef, [[MUL_310]]
|
||||
; SSE2-NEXT: [[MUL_512:%.*]] = xor i32 undef, [[MUL_411]]
|
||||
; SSE2-NEXT: [[MUL_613:%.*]] = xor i32 undef, [[MUL_512]]
|
||||
; SSE2-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX:%.*]] = xor <8 x i32> [[TMP1]], [[RDX_SHUF]]
|
||||
; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX2:%.*]] = xor <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
|
||||
; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE2-NEXT: [[BIN_RDX4:%.*]] = xor <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
|
||||
; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
|
||||
; SSE2-NEXT: [[MUL_714:%.*]] = xor i32 undef, [[MUL_613]]
|
||||
; SSE2-NEXT: ret i32 [[TMP2]]
|
||||
; SSE-LABEL: @test_xor(
|
||||
; SSE-NEXT: entry:
|
||||
; SSE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[P:%.*]], i64 1
|
||||
; SSE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 2
|
||||
; SSE-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 3
|
||||
; SSE-NEXT: [[ARRAYIDX_4:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 4
|
||||
; SSE-NEXT: [[ARRAYIDX_5:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 5
|
||||
; SSE-NEXT: [[ARRAYIDX_6:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 6
|
||||
; SSE-NEXT: [[ARRAYIDX_7:%.*]] = getelementptr inbounds i32, i32* [[P]], i64 7
|
||||
; SSE-NEXT: [[TMP0:%.*]] = bitcast i32* [[P]] to <8 x i32>*
|
||||
; SSE-NEXT: [[TMP1:%.*]] = load <8 x i32>, <8 x i32>* [[TMP0]], align 4
|
||||
; SSE-NEXT: [[MUL_18:%.*]] = xor i32 undef, undef
|
||||
; SSE-NEXT: [[MUL_29:%.*]] = xor i32 undef, [[MUL_18]]
|
||||
; SSE-NEXT: [[MUL_310:%.*]] = xor i32 undef, [[MUL_29]]
|
||||
; SSE-NEXT: [[MUL_411:%.*]] = xor i32 undef, [[MUL_310]]
|
||||
; SSE-NEXT: [[MUL_512:%.*]] = xor i32 undef, [[MUL_411]]
|
||||
; SSE-NEXT: [[MUL_613:%.*]] = xor i32 undef, [[MUL_512]]
|
||||
; SSE-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX:%.*]] = xor <8 x i32> [[TMP1]], [[RDX_SHUF]]
|
||||
; SSE-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX2:%.*]] = xor <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
|
||||
; SSE-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||
; SSE-NEXT: [[BIN_RDX4:%.*]] = xor <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
|
||||
; SSE-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
|
||||
; SSE-NEXT: [[MUL_714:%.*]] = xor i32 undef, [[MUL_613]]
|
||||
; SSE-NEXT: ret i32 [[TMP2]]
|
||||
;
|
||||
entry:
|
||||
%0 = load i32, i32* %p, align 4
|
||||
|
|
@ -441,3 +388,42 @@ entry:
|
|||
%mul.714 = xor i32 %7, %mul.613
|
||||
ret i32 %mul.714
|
||||
}
|
||||
|
||||
define i32 @PR37731(<4 x i32>* noalias nocapture dereferenceable(16) %self) unnamed_addr #0 {
|
||||
; CHECK-LABEL: @PR37731(
|
||||
; CHECK-NEXT: entry:
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[SELF:%.*]], align 16
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[TMP0]], <i32 6, i32 2, i32 13, i32 3>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = xor <4 x i32> [[TMP1]], [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP2]], <i32 13, i32 27, i32 21, i32 12>
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i32> [[TMP0]], <i32 -2, i32 -8, i32 -16, i32 -128>
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i32> [[TMP4]], <i32 18, i32 2, i32 7, i32 13>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = xor <4 x i32> [[TMP3]], [[TMP5]]
|
||||
; CHECK-NEXT: store <4 x i32> [[TMP6]], <4 x i32>* [[SELF]], align 16
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[TMP6]], i32 1
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP7]], [[TMP8]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i32> [[TMP6]], i32 2
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = xor i32 [[TMP9]], [[TMP10]]
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[TMP6]], i32 3
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = xor i32 [[TMP11]], [[TMP12]]
|
||||
; CHECK-NEXT: ret i32 [[TMP13]]
|
||||
;
|
||||
entry:
|
||||
%0 = load <4 x i32>, <4 x i32>* %self, align 16
|
||||
%1 = shl <4 x i32> %0, <i32 6, i32 2, i32 13, i32 3>
|
||||
%2 = xor <4 x i32> %1, %0
|
||||
%3 = lshr <4 x i32> %2, <i32 13, i32 27, i32 21, i32 12>
|
||||
%4 = and <4 x i32> %0, <i32 -2, i32 -8, i32 -16, i32 -128>
|
||||
%5 = shl <4 x i32> %4, <i32 18, i32 2, i32 7, i32 13>
|
||||
%6 = xor <4 x i32> %3, %5
|
||||
store <4 x i32> %6, <4 x i32>* %self, align 16
|
||||
%7 = extractelement <4 x i32> %6, i32 0
|
||||
%8 = extractelement <4 x i32> %6, i32 1
|
||||
%9 = xor i32 %7, %8
|
||||
%10 = extractelement <4 x i32> %6, i32 2
|
||||
%11 = xor i32 %9, %10
|
||||
%12 = extractelement <4 x i32> %6, i32 3
|
||||
%13 = xor i32 %11, %12
|
||||
ret i32 %13
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue