forked from OSchip/llvm-project
[PowerPC] Support register name prefixes for vector registers
Match binutils by supporting the optional register name prefix for new vector registers ("vs" for VSX registers and "q" for QPX registers). llvm-svn: 235665
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@ -1219,10 +1219,18 @@ MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
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!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
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RegNo = FRegs[IntVal];
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return false;
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} else if (Name.startswith_lower("vs") &&
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!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
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RegNo = VSRegs[IntVal];
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return false;
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} else if (Name.startswith_lower("v") &&
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!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
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RegNo = VRegs[IntVal];
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return false;
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} else if (Name.startswith_lower("q") &&
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!Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
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RegNo = QFRegs[IntVal];
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return false;
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} else if (Name.startswith_lower("cr") &&
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!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
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RegNo = CRRegs[IntVal];
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@ -1,6 +1,7 @@
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# RUN: llvm-mc -triple powerpc64-bgq-linux --show-encoding %s | FileCheck %s
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# FIXME: print qvflogical aliases.
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# CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10]
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qvfabs %q3, %q5
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# CHECK: qvfabs 3, 5 # encoding: [0x10,0x60,0x2a,0x10]
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qvfabs 3, 5
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@ -1,6 +1,10 @@
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# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
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# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
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# CHECK-BE: xxswapd 7, 63 # encoding: [0xf0,0xff,0xfa,0x56]
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# CHECK-LE: xxswapd 7, 63 # encoding: [0x56,0xfa,0xff,0xf0]
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xxswapd %vs7, %vs63
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# CHECK-BE: lxsdx 39, 5, 31 # encoding: [0x7c,0xe5,0xfc,0x99]
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# CHECK-LE: lxsdx 39, 5, 31 # encoding: [0x99,0xfc,0xe5,0x7c]
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lxsdx 39, 5, 31
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