forked from OSchip/llvm-project
Remove pseudo instructions that are no longer used.
llvm-svn: 157492
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parent
e99b084cd7
commit
4d9b017ef2
llvm/lib/Target/Mips
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@ -67,12 +67,6 @@ bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) {
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default:
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default:
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++I;
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++I;
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continue;
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continue;
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case Mips::SETGP2:
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// Convert "setgp2 $globalreg, $t9" to "addu $globalreg, $v0, $t9"
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BuildMI(MBB, I, I->getDebugLoc(), TII->get(Mips::ADDu),
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I->getOperand(0).getReg())
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.addReg(Mips::V0).addReg(I->getOperand(1).getReg());
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break;
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case Mips::BuildPairF64:
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case Mips::BuildPairF64:
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ExpandBuildPairF64(MBB, I);
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ExpandBuildPairF64(MBB, I);
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break;
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break;
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@ -796,29 +796,6 @@ let neverHasSideEffects = 1 in
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
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def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
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".cprestore\t$loc", []>;
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".cprestore\t$loc", []>;
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// For O32 ABI & PIC & non-fixed global base register, the following instruction
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// seqeunce is emitted to set the global base register:
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//
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// 0. lui $2, %hi(_gp_disp)
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// 1. addiu $2, $2, %lo(_gp_disp)
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// 2. addu $globalbasereg, $2, $t9
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//
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// SETGP01 is emitted during Prologue/Epilogue insertion and then converted to
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// instructions 0 and 1 in the sequence above during MC lowering.
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// SETGP2 is emitted just before register allocation and converted to
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// instruction 2 just prior to post-RA scheduling.
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//
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// These pseudo instructions are needed to ensure no instructions are inserted
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// before or between instructions 0 and 1, which is a limitation imposed by
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// GNU linker.
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let isTerminator = 1, isBarrier = 1 in
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def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
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let neverHasSideEffects = 1 in
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def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
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[]>;
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let usesCustomInserter = 1 in {
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let usesCustomInserter = 1 in {
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defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
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defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
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defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
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defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
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