forked from OSchip/llvm-project
[NFC][libc] rearrange aarch64 memset code to better match new implementation
Differential Revision: https://reviews.llvm.org/D132121
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@ -52,8 +52,9 @@ using _4 = __llvm_libc::scalar::_4;
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using _32 = Chained<_16, _16>;
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using _64 = Chained<_32, _32>;
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struct ZVA {
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struct Zva64 {
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static constexpr size_t SIZE = 64;
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static void splat_set(char *dst, const unsigned char) {
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#if __SIZEOF_POINTER__ == 4
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asm("dc zva, %w[dst]" : : [dst] "r"(dst) : "memory");
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@ -63,13 +64,14 @@ struct ZVA {
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}
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};
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inline static bool AArch64ZVA(char *dst, size_t count) {
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inline static bool hasZva() {
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uint64_t zva_val;
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asm("mrs %[zva_val], dczid_el0" : [zva_val] "=r"(zva_val));
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if ((zva_val & 31) != 4)
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return false;
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splat_set<Align<_64, Arg::_1>::Then<Loop<ZVA, _64>>>(dst, 0, count);
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return true;
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// DC ZVA is permitted if DZP, bit [4] is zero.
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// BS, bits [3:0] is log2 of the block size in words.
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// So the next line checks whether the instruction is permitted and block size
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// is 16 words (i.e. 64 bytes).
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return (zva_val & 0b11111) == 0b00100;
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}
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} // namespace aarch64_memset
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@ -92,7 +92,7 @@ inline static void inline_memset(char *dst, unsigned char value, size_t count) {
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return splat_set<HeadTail<_8>>(dst, value, count);
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if (count <= 32)
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return splat_set<HeadTail<_16>>(dst, value, count);
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if (count <= 96) {
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if (count <= (32 + 64)) {
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splat_set<_32>(dst, value);
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if (count <= 64)
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return splat_set<Tail<_32>>(dst, value, count);
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@ -100,7 +100,9 @@ inline static void inline_memset(char *dst, unsigned char value, size_t count) {
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splat_set<Tail<_32>>(dst, value, count);
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return;
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}
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if (count < 448 || value != 0 || !AArch64ZVA(dst, count))
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if (count >= 448 && value == 0 && hasZva())
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return splat_set<Align<_64, Arg::_1>::Then<Loop<Zva64>>>(dst, 0, count);
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else
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return splat_set<Align<_16, Arg::_1>::Then<Loop<_64>>>(dst, value, count);
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#else
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/////////////////////////////////////////////////////////////////////////////
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