forked from OSchip/llvm-project
Renamed files to match the primary classes they provide.
llvm-svn: 620
This commit is contained in:
Vikram S. Adve
parent
8dd5e310e0
commit
4d86cc2842
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@ -1,84 +0,0 @@
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//===-- llvm/Target/Data.h - Data size & alignment routines ------*- C++ -*-==//
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//
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// This file defines target properties related to datatype size/offset/alignment
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// information. It uses lazy annotations to cache information about how
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// structure types are laid out and used.
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//
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// This structure should be created once, filled in if the defaults are not
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// correct and then passed around by const&. None of the members functions
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// require modification to the object.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_DATA_H
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#define LLVM_TARGET_DATA_H
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#include "llvm/Type.h"
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class StructType;
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class StructLayout;
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class TargetData {
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unsigned char ByteAlignment; // Defaults to 1 bytes
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unsigned char ShortAlignment; // Defaults to 2 bytes
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unsigned char IntAlignment; // Defaults to 4 bytes
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unsigned char LongAlignment; // Defaults to 8 bytes
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unsigned char FloatAlignment; // Defaults to 4 bytes
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unsigned char DoubleAlignment; // Defaults to 8 bytes
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unsigned char PointerSize; // Defaults to 8 bytes
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unsigned char PointerAlignment; // Defaults to 8 bytes
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AnnotationID AID; // AID for structure layout annotation
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static Annotation *TypeAnFactory(AnnotationID, const Annotable *, void *);
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public:
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TargetData(const string &TargetName, unsigned char PtrSize = 8,
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unsigned char PtrAl = 8, unsigned char DoubleAl = 8,
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unsigned char FloatAl = 4, unsigned char LongAl = 8,
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unsigned char IntAl = 4, unsigned char ShortAl = 2,
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unsigned char ByteAl = 1);
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~TargetData(); // Not virtual, do not subclass this class
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unsigned char getByteAlignment() const { return ByteAlignment; }
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unsigned char getShortAlignment() const { return ShortAlignment; }
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unsigned char getIntAlignment() const { return IntAlignment; }
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unsigned char getLongAlignment() const { return LongAlignment; }
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unsigned char getFloatAlignment() const { return FloatAlignment; }
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unsigned char getDoubleAlignment() const { return DoubleAlignment; }
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unsigned char getPointerAlignment() const { return PointerAlignment; }
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unsigned char getPointerSize() const { return PointerSize; }
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AnnotationID getStructLayoutAID() const { return AID; }
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// getTypeSize - Return the number of bytes neccesary to hold the specified
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// type
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unsigned getTypeSize (const Type *Ty) const;
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// getTypeAlignment - Return the minimum required alignment for the specified
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// type
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unsigned char getTypeAlignment(const Type *Ty) const;
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// getIndexOffset - return the offset from the beginning of the type for the
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// specified indices. This is used to implement getElementPtr and load and
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// stores that include the implicit form of getelementptr.
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//
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unsigned getIndexedOffset(const Type *Ty,
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const vector<ConstPoolVal*> &Indices) const;
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inline const StructLayout *getStructLayout(const StructType *Ty) const {
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return (const StructLayout*)((const Type*)Ty)->getOrCreateAnnotation(AID);
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}
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};
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// This annotation (attached ONLY to StructType classes) is used to lazily
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// calculate structure layout information for a target machine, based on the
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// TargetData structure.
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//
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struct StructLayout : public Annotation {
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vector<unsigned> MemberOffsets;
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unsigned StructSize;
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unsigned StructAlignment;
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private:
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friend class TargetData; // Only TargetData can create this class
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inline StructLayout(const StructType *ST, const TargetData &TD);
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};
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#endif
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@ -1,216 +0,0 @@
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//===-- llvm/Target/InstInfo.h - Target Instruction Information --*- C++ -*-==//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_INSTINFO_H
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#define LLVM_TARGET_INSTINFO_H
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#include "llvm/Target/Machine.h"
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#include "llvm/Support/DataTypes.h"
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class MachineInstrDescriptor;
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typedef int InstrSchedClass;
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class MachineInstrInfo.
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//
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// FIXME: This should be a property of the target so that more than one target
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// at a time can be active...
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//
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extern const MachineInstrDescriptor *TargetInstrDescriptors;
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//---------------------------------------------------------------------------
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// struct MachineInstrDescriptor:
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// Predefined information about each machine instruction.
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// Designed to initialized statically.
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//
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// class MachineInstructionInfo
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// Interface to description of machine instructions
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//
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//---------------------------------------------------------------------------
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const unsigned int M_NOP_FLAG = 1;
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const unsigned int M_BRANCH_FLAG = 1 << 1;
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const unsigned int M_CALL_FLAG = 1 << 2;
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const unsigned int M_RET_FLAG = 1 << 3;
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const unsigned int M_ARITH_FLAG = 1 << 4;
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const unsigned int M_CC_FLAG = 1 << 6;
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const unsigned int M_LOGICAL_FLAG = 1 << 6;
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const unsigned int M_INT_FLAG = 1 << 7;
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const unsigned int M_FLOAT_FLAG = 1 << 8;
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const unsigned int M_CONDL_FLAG = 1 << 9;
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const unsigned int M_LOAD_FLAG = 1 << 10;
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const unsigned int M_PREFETCH_FLAG = 1 << 11;
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const unsigned int M_STORE_FLAG = 1 << 12;
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const unsigned int M_DUMMY_PHI_FLAG = 1 << 13;
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struct MachineInstrDescriptor {
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string opCodeString; // Assembly language mnemonic for the opcode.
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int numOperands; // Number of args; -1 if variable #args
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int resultPos; // Position of the result; -1 if no result
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unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
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bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
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// smallest -ve value is -(maxImmedConst+1).
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unsigned int numDelaySlots; // Number of delay slots after instruction
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unsigned int latency; // Latency in machine cycles
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InstrSchedClass schedClass; // enum identifying instr sched class
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unsigned int iclass; // flags identifying machine instr class
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};
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class MachineInstrInfo : public NonCopyableV {
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protected:
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const MachineInstrDescriptor* desc; // raw array to allow static init'n
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unsigned int descSize; // number of entries in the desc array
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unsigned int numRealOpCodes; // number of non-dummy op codes
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public:
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MachineInstrInfo(const MachineInstrDescriptor *desc, unsigned descSize,
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unsigned numRealOpCodes);
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virtual ~MachineInstrInfo();
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unsigned getNumRealOpCodes() const { return numRealOpCodes; }
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unsigned getNumTotalOpCodes() const { return descSize; }
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const MachineInstrDescriptor& getDescriptor(MachineOpCode opCode) const {
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assert(opCode >= 0 && opCode < (int)descSize);
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return desc[opCode];
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}
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int getNumOperands(MachineOpCode opCode) const {
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return getDescriptor(opCode).numOperands;
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}
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int getResultPos(MachineOpCode opCode) const {
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return getDescriptor(opCode).resultPos;
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}
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unsigned getNumDelaySlots(MachineOpCode opCode) const {
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return getDescriptor(opCode).numDelaySlots;
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}
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InstrSchedClass getSchedClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).schedClass;
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}
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//
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// Query instruction class flags according to the machine-independent
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// flags listed above.
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//
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unsigned int getIClass(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass;
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}
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bool isNop(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_NOP_FLAG;
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}
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bool isBranch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG;
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}
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bool isCall(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CALL_FLAG;
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}
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bool isReturn(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isControlFlow(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_BRANCH_FLAG
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|| getDescriptor(opCode).iclass & M_CALL_FLAG
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|| getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isArith(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_RET_FLAG;
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}
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bool isCCInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CC_FLAG;
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}
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bool isLogical(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOGICAL_FLAG;
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}
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bool isIntInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_INT_FLAG;
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}
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bool isFloatInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_FLOAT_FLAG;
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}
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bool isConditional(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_CONDL_FLAG;
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}
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bool isLoad(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG;
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}
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bool isPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isLoadOrPrefetch(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG;
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}
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bool isStore(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isMemoryAccess(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_LOAD_FLAG
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|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
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|| getDescriptor(opCode).iclass & M_STORE_FLAG;
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}
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bool isDummyPhiInstr(MachineOpCode opCode) const {
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return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
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}
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// delete this later *******
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bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
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// Check if an instruction can be issued before its operands are ready,
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// or if a subsequent instruction that uses its result can be issued
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// before the results are ready.
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// Default to true since most instructions on many architectures allow this.
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//
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virtual bool hasOperandInterlock(MachineOpCode opCode) const {
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return true;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const {
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return true;
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}
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//
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// Latencies for individual instructions and instruction pairs
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//
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virtual int minLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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virtual int maxLatency(MachineOpCode opCode) const {
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return getDescriptor(opCode).latency;
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}
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// Check if the specified constant fits in the immediate field
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// of this machine instruction
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//
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virtual bool constantFitsInImmedField(MachineOpCode opCode,
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int64_t intValue) const;
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// Return the largest +ve constant that can be held in the IMMMED field
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// of this machine instruction.
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// isSignExtended is set to true if the value is sign-extended before use
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// (this is true for all immediate fields in SPARC instructions).
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// Return 0 if the instruction has no IMMED field.
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//
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virtual uint64_t maxImmedConstant(MachineOpCode opCode,
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bool &isSignExtended) const {
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isSignExtended = getDescriptor(opCode).immedIsSignExtended;
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return getDescriptor(opCode).maxImmedConst;
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}
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};
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#endif
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@ -1,84 +0,0 @@
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//===-- llvm/Target/Machine.h - General Target Information -------*- C++ -*-==//
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//
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// This file describes the general parts of a Target machine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_MACHINE_H
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#define LLVM_TARGET_MACHINE_H
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#include "llvm/Target/Data.h"
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#include "llvm/Support/NonCopyable.h"
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#include <string>
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class TargetMachine;
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class MachineInstrInfo;
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class MachineInstrDescriptor;
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class MachineRegInfo;
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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typedef int MachineOpCode;
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typedef int OpCodeMask;
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//---------------------------------------------------------------------------
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// class TargetMachine
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//
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// Purpose:
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// Primary interface to machine description for the target machine.
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//
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//---------------------------------------------------------------------------
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class TargetMachine : public NonCopyableV {
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public:
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const string TargetName;
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const TargetData DataLayout; // Calculates type size & alignment
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int optSizeForSubWordData;
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int minMemOpWordSize;
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int maxAtomicMemOpWordSize;
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// Register information. This needs to be reorganized into a single class.
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int zeroRegNum; // register that gives 0 if any (-1 if none)
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protected:
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TargetMachine(const string &targetname, // Can only create subclasses...
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unsigned char PtrSize = 8, unsigned char PtrAl = 8,
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unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
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unsigned char LongAl = 8, unsigned char IntAl = 4,
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unsigned char ShortAl = 2, unsigned char ByteAl = 1)
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: TargetName(targetname), DataLayout(targetname, PtrSize, PtrAl,
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DoubleAl, FloatAl, LongAl, IntAl,
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ShortAl, ByteAl) { }
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public:
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virtual ~TargetMachine() {}
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virtual const MachineInstrInfo& getInstrInfo() const = 0;
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virtual const MachineRegInfo& getRegInfo() const = 0;
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virtual unsigned int findOptimalStorageSize (const Type* ty) const;
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// This really should be in the register info class
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virtual bool regsMayBeAliased (unsigned int regNum1,
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unsigned int regNum2) const {
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return (regNum1 == regNum2);
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}
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// compileMethod - This does everything neccesary to compile a method into the
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// built in representation. This allows the target to have complete control
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// over how it does compilation. This does not emit assembly or output
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// machine code however, this is done later.
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//
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virtual bool compileMethod(Method *M) = 0;
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// emitAssembly - Output assembly language code (a .s file) for the specified
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// method. The specified method must have been compiled before this may be
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// used.
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//
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virtual void emitAssembly(Method *M, ostream &OutStr) { /* todo */ }
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};
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#endif
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@ -1,234 +0,0 @@
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//===-- llvm/Target/RegInfo.h - Target Register Information ------*- C++ -*-==//
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//
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// This file is used to describe the register system of a target to the register
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// allocator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_REGINFO_H
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#define LLVM_TARGET_REGINFO_H
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#include "llvm/Support/NonCopyable.h"
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#include <hash_map>
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#include <string>
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class IGNode;
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class Value;
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class LiveRangeInfo;
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class Method;
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class Instruction;
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class LiveRange;
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class AddedInstrns;
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class MachineInstr;
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//-----------------------------------------------------------------------------
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// class MachineRegClassInfo
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//
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// Purpose:
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// Interface to description of machine register class (e.g., int reg class
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// float reg class etc)
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//
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//--------------------------------------------------------------------------
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class MachineRegClassInfo {
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protected:
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const unsigned RegClassID; // integer ID of a reg class
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const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
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const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
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public:
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inline unsigned getRegClassID() const { return RegClassID; }
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inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
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inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; }
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// This method should find a color which is not used by neighbors
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// (i.e., a false position in IsColorUsedArr) and
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virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
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MachineRegClassInfo(const unsigned ID, const unsigned NVR,
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const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
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NumOfAllRegs(NAR)
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{ } // empty constructor
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};
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//---------------------------------------------------------------------------
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// class MachineRegInfo
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//
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// Purpose:
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// Interface to register info of target machine
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//
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//--------------------------------------------------------------------------
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typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
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// A vector of all machine register classes
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typedef vector<const MachineRegClassInfo *> MachineRegClassArrayType;
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class MachineRegInfo : public NonCopyableV {
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protected:
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MachineRegClassArrayType MachineRegClassArr;
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public:
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// According the definition of a MachineOperand class, a Value in a
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// machine instruction can go into either a normal register or a
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// condition code register. If isCCReg is true below, the ID of the condition
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// code regiter class will be returned. Otherwise, the normal register
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// class (eg. int, float) must be returned.
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virtual unsigned getRegClassIDOfValue (const Value *const Val,
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bool isCCReg = false) const =0;
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inline unsigned int getNumOfRegClasses() const {
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return MachineRegClassArr.size();
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}
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const MachineRegClassInfo *const getMachineRegClass(unsigned i) const {
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return MachineRegClassArr[i];
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}
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|
||||
//virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0;
|
||||
// this method must give the exact register class of a machine operand
|
||||
// e.g, Int, Float, Int CC, Float CC
|
||||
//virtual unsigned getRCIDOfMachineOp (const MachineOperand &MO) const = 0;
|
||||
|
||||
|
||||
virtual void colorArgs(const Method *const Meth,
|
||||
LiveRangeInfo & LRI) const = 0;
|
||||
|
||||
virtual void colorCallArgs(vector<const Instruction *> & CallInstrList,
|
||||
LiveRangeInfo& LRI,
|
||||
AddedInstrMapType& AddedInstrMap ) const = 0 ;
|
||||
|
||||
virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0;
|
||||
|
||||
virtual const string getUnifiedRegName(int UnifiedRegNum) const = 0;
|
||||
|
||||
//virtual void printReg(const LiveRange *const LR) const =0;
|
||||
|
||||
MachineRegInfo() { }
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#if 0
|
||||
|
||||
class Value;
|
||||
class Instruction;
|
||||
class Method;
|
||||
class LiveRangeInfo;
|
||||
class LiveRange;
|
||||
class AddedInstrns;
|
||||
class MachineInstr;
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// class MachineRegClassInfo
|
||||
//
|
||||
// Purpose:
|
||||
// Interface to description of machine register class (e.g., int reg class
|
||||
// float reg class etc)
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
class IGNode;
|
||||
class MachineRegClassInfo {
|
||||
protected:
|
||||
const unsigned RegClassID; // integer ID of a reg class
|
||||
const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
|
||||
const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
|
||||
|
||||
public:
|
||||
|
||||
inline unsigned getRegClassID() const { return RegClassID; }
|
||||
inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
|
||||
inline unsigned getNumOfAllRegs() const { return NumOfAllRegs; }
|
||||
|
||||
|
||||
|
||||
// This method should find a color which is not used by neighbors
|
||||
// (i.e., a false position in IsColorUsedArr) and
|
||||
virtual void colorIGNode(IGNode * Node, bool IsColorUsedArr[] ) const = 0;
|
||||
|
||||
|
||||
MachineRegClassInfo(const unsigned ID, const unsigned NVR,
|
||||
const unsigned NAR): RegClassID(ID), NumOfAvailRegs(NVR),
|
||||
NumOfAllRegs(NAR) { }
|
||||
};
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineRegInfo
|
||||
//
|
||||
// Purpose:
|
||||
// Interface to register info of target machine
|
||||
//
|
||||
//--------------------------------------------------------------------------
|
||||
|
||||
typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
|
||||
|
||||
// A vector of all machine register classestypedef vector<const MachineRegClassInfo *> MachineRegClassArrayType;
|
||||
|
||||
|
||||
class MachineRegInfo : public NonCopyableV {
|
||||
protected:
|
||||
MachineRegClassArrayType MachineRegClassArr;
|
||||
|
||||
public:
|
||||
inline unsigned int getNumOfRegClasses() const {
|
||||
return MachineRegClassArr.size();
|
||||
}
|
||||
|
||||
const MachineRegClassInfo *const getMachineRegClass(unsigned i) const {
|
||||
return MachineRegClassArr[i];
|
||||
}
|
||||
|
||||
|
||||
virtual unsigned getRegClassIDOfValue (const Value *const Val) const = 0;
|
||||
|
||||
virtual void colorArgs(const Method *const Meth,
|
||||
LiveRangeInfo & LRI) const = 0;
|
||||
|
||||
virtual void colorCallArgs(vector<const Instruction *> & CallInstrList,
|
||||
LiveRangeInfo& LRI,
|
||||
AddedInstrMapType& AddedInstrMap ) const = 0;
|
||||
|
||||
virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0;
|
||||
|
||||
virtual const string getUnifiedRegName(int reg) const = 0;
|
||||
|
||||
//virtual void printReg(const LiveRange *const LR) const =0;
|
||||
|
||||
MachineRegInfo() { }
|
||||
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -1,396 +0,0 @@
|
|||
//===-- llvm/Target/SchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
|
||||
//
|
||||
// This file describes the target machine to the instruction scheduler.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_TARGET_SCHEDINFO_H
|
||||
#define LLVM_TARGET_SCHEDINFO_H
|
||||
|
||||
#include "llvm/Target/InstInfo.h"
|
||||
#include <hash_map>
|
||||
|
||||
typedef long long cycles_t;
|
||||
const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-1);
|
||||
const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
|
||||
static const unsigned MAX_OPCODE_SIZE = 16;
|
||||
|
||||
class OpCodePair {
|
||||
public:
|
||||
long val; // make long by concatenating two opcodes
|
||||
OpCodePair(MachineOpCode op1, MachineOpCode op2)
|
||||
: val((op1 < 0 || op2 < 0)?
|
||||
-1 : (long)((((unsigned) op1) << MAX_OPCODE_SIZE) | (unsigned) op2)) {}
|
||||
bool operator==(const OpCodePair& op) const {
|
||||
return val == op.val;
|
||||
}
|
||||
private:
|
||||
OpCodePair(); // disable for now
|
||||
};
|
||||
|
||||
|
||||
template <> struct hash<OpCodePair> {
|
||||
size_t operator()(const OpCodePair& pair) const {
|
||||
return hash<long>()(pair.val);
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineResource
|
||||
// class CPUResource
|
||||
//
|
||||
// Purpose:
|
||||
// Representation of a single machine resource used in specifying
|
||||
// resource usages of machine instructions for scheduling.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
|
||||
typedef unsigned int resourceId_t;
|
||||
|
||||
class MachineResource {
|
||||
public:
|
||||
const string rname;
|
||||
resourceId_t rid;
|
||||
|
||||
/*ctor*/ MachineResource(const string& resourceName)
|
||||
: rname(resourceName), rid(nextId++) {}
|
||||
|
||||
private:
|
||||
static resourceId_t nextId;
|
||||
MachineResource(); // disable
|
||||
};
|
||||
|
||||
|
||||
class CPUResource : public MachineResource {
|
||||
public:
|
||||
int maxNumUsers; // MAXINT if no restriction
|
||||
|
||||
/*ctor*/ CPUResource(const string& rname, int maxUsers)
|
||||
: MachineResource(rname), maxNumUsers(maxUsers) {}
|
||||
};
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// struct InstrClassRUsage
|
||||
// struct InstrRUsageDelta
|
||||
// struct InstrIssueDelta
|
||||
// struct InstrRUsage
|
||||
//
|
||||
// Purpose:
|
||||
// The first three are structures used to specify machine resource
|
||||
// usages for each instruction in a machine description file:
|
||||
// InstrClassRUsage : resource usages common to all instrs. in a class
|
||||
// InstrRUsageDelta : add/delete resource usage for individual instrs.
|
||||
// InstrIssueDelta : add/delete instr. issue info for individual instrs
|
||||
//
|
||||
// The last one (InstrRUsage) is the internal representation of
|
||||
// instruction resource usage constructed from the above three.
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
const int MAX_NUM_SLOTS = 32;
|
||||
const int MAX_NUM_CYCLES = 32;
|
||||
|
||||
struct InstrClassRUsage {
|
||||
InstrSchedClass schedClass;
|
||||
int totCycles;
|
||||
|
||||
// Issue restrictions common to instructions in this class
|
||||
unsigned int maxNumIssue;
|
||||
bool isSingleIssue;
|
||||
bool breaksGroup;
|
||||
cycles_t numBubbles;
|
||||
|
||||
// Feasible slots to use for instructions in this class.
|
||||
// The size of vector S[] is `numSlots'.
|
||||
unsigned int numSlots;
|
||||
unsigned int feasibleSlots[MAX_NUM_SLOTS];
|
||||
|
||||
// Resource usages common to instructions in this class.
|
||||
// The size of vector V[] is `numRUEntries'.
|
||||
unsigned int numRUEntries;
|
||||
struct {
|
||||
resourceId_t resourceId;
|
||||
unsigned int startCycle;
|
||||
int numCycles;
|
||||
} V[MAX_NUM_CYCLES];
|
||||
};
|
||||
|
||||
struct InstrRUsageDelta {
|
||||
MachineOpCode opCode;
|
||||
resourceId_t resourceId;
|
||||
unsigned int startCycle;
|
||||
int numCycles;
|
||||
};
|
||||
|
||||
// Specify instruction issue restrictions for individual instructions
|
||||
// that differ from the common rules for the class.
|
||||
//
|
||||
struct InstrIssueDelta {
|
||||
MachineOpCode opCode;
|
||||
bool isSingleIssue;
|
||||
bool breaksGroup;
|
||||
cycles_t numBubbles;
|
||||
};
|
||||
|
||||
|
||||
struct InstrRUsage {
|
||||
/*ctor*/ InstrRUsage () {}
|
||||
/*ctor*/ InstrRUsage (const InstrRUsage& instrRU);
|
||||
InstrRUsage& operator= (const InstrRUsage& instrRU);
|
||||
|
||||
bool sameAsClass;
|
||||
|
||||
// Issue restrictions for this instruction
|
||||
bool isSingleIssue;
|
||||
bool breaksGroup;
|
||||
cycles_t numBubbles;
|
||||
|
||||
// Feasible slots to use for this instruction.
|
||||
vector<bool> feasibleSlots;
|
||||
|
||||
// Resource usages for this instruction, with one resource vector per cycle.
|
||||
cycles_t numCycles;
|
||||
vector<vector<resourceId_t> > resourcesByCycle;
|
||||
|
||||
private:
|
||||
// Conveniences for initializing this structure
|
||||
InstrRUsage& operator= (const InstrClassRUsage& classRU);
|
||||
void addIssueDelta (const InstrIssueDelta& delta);
|
||||
void addUsageDelta (const InstrRUsageDelta& delta);
|
||||
void setMaxSlots (int maxNumSlots);
|
||||
|
||||
friend class MachineSchedInfo; // give access to these functions
|
||||
};
|
||||
|
||||
|
||||
inline void
|
||||
InstrRUsage::setMaxSlots(int maxNumSlots)
|
||||
{
|
||||
feasibleSlots.resize(maxNumSlots);
|
||||
}
|
||||
|
||||
inline InstrRUsage&
|
||||
InstrRUsage::operator=(const InstrRUsage& instrRU)
|
||||
{
|
||||
sameAsClass = instrRU.sameAsClass;
|
||||
isSingleIssue = instrRU.isSingleIssue;
|
||||
breaksGroup = instrRU.breaksGroup;
|
||||
numBubbles = instrRU.numBubbles;
|
||||
feasibleSlots = instrRU.feasibleSlots;
|
||||
numCycles = instrRU.numCycles;
|
||||
resourcesByCycle = instrRU.resourcesByCycle;
|
||||
return *this;
|
||||
}
|
||||
|
||||
inline /*ctor*/
|
||||
InstrRUsage::InstrRUsage(const InstrRUsage& instrRU)
|
||||
{
|
||||
*this = instrRU;
|
||||
}
|
||||
|
||||
inline InstrRUsage&
|
||||
InstrRUsage::operator=(const InstrClassRUsage& classRU)
|
||||
{
|
||||
sameAsClass = true;
|
||||
isSingleIssue = classRU.isSingleIssue;
|
||||
breaksGroup = classRU.breaksGroup;
|
||||
numBubbles = classRU.numBubbles;
|
||||
|
||||
for (unsigned i=0; i < classRU.numSlots; i++)
|
||||
{
|
||||
unsigned slot = classRU.feasibleSlots[i];
|
||||
assert(slot < feasibleSlots.size() && "Invalid slot specified!");
|
||||
this->feasibleSlots[slot] = true;
|
||||
}
|
||||
|
||||
this->numCycles = classRU.totCycles;
|
||||
this->resourcesByCycle.resize(this->numCycles);
|
||||
|
||||
for (unsigned i=0; i < classRU.numRUEntries; i++)
|
||||
for (unsigned c=classRU.V[i].startCycle, NC = c + classRU.V[i].numCycles;
|
||||
c < NC; c++)
|
||||
this->resourcesByCycle[c].push_back(classRU.V[i].resourceId);
|
||||
|
||||
// Sort each resource usage vector by resourceId_t to speed up conflict checking
|
||||
for (unsigned i=0; i < this->resourcesByCycle.size(); i++)
|
||||
sort(resourcesByCycle[i].begin(), resourcesByCycle[i].end());
|
||||
|
||||
return *this;
|
||||
}
|
||||
|
||||
|
||||
inline void
|
||||
InstrRUsage::addIssueDelta(const InstrIssueDelta& delta)
|
||||
{
|
||||
sameAsClass = false;
|
||||
isSingleIssue = delta.isSingleIssue;
|
||||
breaksGroup = delta.breaksGroup;
|
||||
numBubbles = delta.numBubbles;
|
||||
}
|
||||
|
||||
|
||||
// Add the extra resource usage requirements specified in the delta.
|
||||
// Note that a negative value of `numCycles' means one entry for that
|
||||
// resource should be deleted for each cycle.
|
||||
//
|
||||
inline void
|
||||
InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
|
||||
{
|
||||
int NC = delta.numCycles;
|
||||
|
||||
this->sameAsClass = false;
|
||||
|
||||
// resize the resources vector if more cycles are specified
|
||||
unsigned maxCycles = this->numCycles;
|
||||
maxCycles = max(maxCycles, delta.startCycle + abs(NC) - 1);
|
||||
if (maxCycles > this->numCycles)
|
||||
{
|
||||
this->resourcesByCycle.resize(maxCycles);
|
||||
this->numCycles = maxCycles;
|
||||
}
|
||||
|
||||
if (NC >= 0)
|
||||
for (unsigned c=delta.startCycle, last=c+NC-1; c <= last; c++)
|
||||
this->resourcesByCycle[c].push_back(delta.resourceId);
|
||||
else
|
||||
// Remove the resource from all NC cycles.
|
||||
for (unsigned c=delta.startCycle, last=(c-NC)-1; c <= last; c++)
|
||||
{
|
||||
// Look for the resource backwards so we remove the last entry
|
||||
// for that resource in each cycle.
|
||||
vector<resourceId_t>& rvec = this->resourcesByCycle[c];
|
||||
int r;
|
||||
for (r = (int) rvec.size(); r >= 0; r--)
|
||||
if (rvec[r] == delta.resourceId)
|
||||
{// found last entry for the resource
|
||||
rvec.erase(rvec.begin() + r);
|
||||
break;
|
||||
}
|
||||
assert(r >= 0 && "Resource to remove was unused in cycle c!");
|
||||
}
|
||||
}
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineSchedInfo
|
||||
//
|
||||
// Purpose:
|
||||
// Common interface to machine information for instruction scheduling
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
class MachineSchedInfo : public NonCopyableV {
|
||||
public:
|
||||
unsigned int maxNumIssueTotal;
|
||||
int longestIssueConflict;
|
||||
|
||||
int branchMispredictPenalty; // 4 for SPARC IIi
|
||||
int branchTargetUnknownPenalty; // 2 for SPARC IIi
|
||||
int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
|
||||
int l1ICacheMissPenalty; // ? for SPARC IIi
|
||||
|
||||
bool inOrderLoads; // true for SPARC IIi
|
||||
bool inOrderIssue; // true for SPARC IIi
|
||||
bool inOrderExec; // false for most architectures
|
||||
bool inOrderRetire; // true for most architectures
|
||||
|
||||
protected:
|
||||
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
|
||||
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
|
||||
return instrRUsages[opCode];
|
||||
}
|
||||
inline const InstrClassRUsage&
|
||||
getClassRUsage(const InstrSchedClass& sc) const {
|
||||
assert(sc >= 0 && sc < numSchedClasses);
|
||||
return classRUsages[sc];
|
||||
}
|
||||
|
||||
public:
|
||||
/*ctor*/ MachineSchedInfo (int _numSchedClasses,
|
||||
const MachineInstrInfo* _mii,
|
||||
const InstrClassRUsage* _classRUsages,
|
||||
const InstrRUsageDelta* _usageDeltas,
|
||||
const InstrIssueDelta* _issueDeltas,
|
||||
unsigned int _numUsageDeltas,
|
||||
unsigned int _numIssueDeltas);
|
||||
/*dtor*/ virtual ~MachineSchedInfo () {}
|
||||
|
||||
inline const MachineInstrInfo& getInstrInfo() const {
|
||||
return *mii;
|
||||
}
|
||||
|
||||
inline int getNumSchedClasses() const {
|
||||
return numSchedClasses;
|
||||
}
|
||||
|
||||
inline unsigned int getMaxNumIssueTotal() const {
|
||||
return maxNumIssueTotal;
|
||||
}
|
||||
|
||||
inline unsigned int getMaxIssueForClass(const InstrSchedClass& sc) const {
|
||||
assert(sc >= 0 && sc < numSchedClasses);
|
||||
return classRUsages[sc].maxNumIssue;
|
||||
}
|
||||
|
||||
inline InstrSchedClass getSchedClass (MachineOpCode opCode) const {
|
||||
return getInstrInfo().getSchedClass(opCode);
|
||||
}
|
||||
|
||||
inline bool instrCanUseSlot (MachineOpCode opCode,
|
||||
unsigned s) const {
|
||||
assert(s < getInstrRUsage(opCode).feasibleSlots.size() && "Invalid slot!");
|
||||
return getInstrRUsage(opCode).feasibleSlots[s];
|
||||
}
|
||||
|
||||
inline int getLongestIssueConflict () const {
|
||||
return longestIssueConflict;
|
||||
}
|
||||
|
||||
inline int getMinIssueGap (MachineOpCode fromOp,
|
||||
MachineOpCode toOp) const {
|
||||
hash_map<OpCodePair,int>::const_iterator
|
||||
I = issueGaps.find(OpCodePair(fromOp, toOp));
|
||||
return (I == issueGaps.end())? 0 : (*I).second;
|
||||
}
|
||||
|
||||
inline const vector<MachineOpCode>*
|
||||
getConflictList(MachineOpCode opCode) const {
|
||||
hash_map<MachineOpCode,vector<MachineOpCode> >::const_iterator
|
||||
I = conflictLists.find(opCode);
|
||||
return (I == conflictLists.end())? NULL : & (*I).second;
|
||||
}
|
||||
|
||||
inline bool isSingleIssue (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).isSingleIssue;
|
||||
}
|
||||
|
||||
inline bool breaksIssueGroup (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).breaksGroup;
|
||||
}
|
||||
|
||||
inline unsigned int numBubblesAfter (MachineOpCode opCode) const {
|
||||
return getInstrRUsage(opCode).numBubbles;
|
||||
}
|
||||
|
||||
protected:
|
||||
virtual void initializeResources ();
|
||||
|
||||
private:
|
||||
void computeInstrResources(const vector<InstrRUsage>& instrRUForClasses);
|
||||
void computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses);
|
||||
|
||||
protected:
|
||||
int numSchedClasses;
|
||||
const MachineInstrInfo* mii;
|
||||
const InstrClassRUsage* classRUsages; // raw array by sclass
|
||||
const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
|
||||
const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
|
||||
unsigned int numUsageDeltas;
|
||||
unsigned int numIssueDeltas;
|
||||
|
||||
vector<InstrRUsage> instrRUsages; // indexed by opcode
|
||||
hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
|
||||
hash_map<MachineOpCode,vector<MachineOpCode> >
|
||||
conflictLists; // indexed by opcode
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -1,175 +0,0 @@
|
|||
//===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
|
||||
//
|
||||
// This file implements the generic part of a Scheduler description for a
|
||||
// target. This functionality is defined in the llvm/Target/SchedInfo.h file.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "llvm/Target/SchedInfo.h"
|
||||
|
||||
// External object describing the machine instructions
|
||||
// Initialized only when the TargetMachine class is created
|
||||
// and reset when that class is destroyed.
|
||||
//
|
||||
const MachineInstrDescriptor* TargetInstrDescriptors = 0;
|
||||
|
||||
resourceId_t MachineResource::nextId = 0;
|
||||
|
||||
// Check if fromRVec and toRVec have *any* common entries.
|
||||
// Assume the vectors are sorted in increasing order.
|
||||
// Algorithm copied from function set_intersection() for sorted ranges
|
||||
// (stl_algo.h).
|
||||
//
|
||||
inline static bool RUConflict(const vector<resourceId_t>& fromRVec,
|
||||
const vector<resourceId_t>& toRVec) {
|
||||
|
||||
unsigned fN = fromRVec.size(), tN = toRVec.size();
|
||||
unsigned fi = 0, ti = 0;
|
||||
|
||||
while (fi < fN && ti < tN) {
|
||||
if (fromRVec[fi] < toRVec[ti])
|
||||
++fi;
|
||||
else if (toRVec[ti] < fromRVec[fi])
|
||||
++ti;
|
||||
else
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
static cycles_t ComputeMinGap(const InstrRUsage &fromRU,
|
||||
const InstrRUsage &toRU) {
|
||||
cycles_t minGap = 0;
|
||||
|
||||
if (fromRU.numBubbles > 0)
|
||||
minGap = fromRU.numBubbles;
|
||||
|
||||
if (minGap < fromRU.numCycles) {
|
||||
// only need to check from cycle `minGap' onwards
|
||||
for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++) {
|
||||
// check if instr. #2 can start executing `gap' cycles after #1
|
||||
// by checking for resource conflicts in each overlapping cycle
|
||||
cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
|
||||
for (cycles_t c = 0; c <= numOverlap-1; c++)
|
||||
if (RUConflict(fromRU.resourcesByCycle[gap + c],
|
||||
toRU.resourcesByCycle[c])) {
|
||||
// conflict found so minGap must be more than `gap'
|
||||
minGap = gap+1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return minGap;
|
||||
}
|
||||
|
||||
|
||||
//---------------------------------------------------------------------------
|
||||
// class MachineSchedInfo
|
||||
// Interface to machine description for instruction scheduling
|
||||
//---------------------------------------------------------------------------
|
||||
|
||||
MachineSchedInfo::MachineSchedInfo(int NumSchedClasses,
|
||||
const MachineInstrInfo* Mii,
|
||||
const InstrClassRUsage* ClassRUsages,
|
||||
const InstrRUsageDelta* UsageDeltas,
|
||||
const InstrIssueDelta* IssueDeltas,
|
||||
unsigned int NumUsageDeltas,
|
||||
unsigned int NumIssueDeltas)
|
||||
: numSchedClasses(NumSchedClasses), mii(Mii),
|
||||
classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
|
||||
issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
|
||||
numIssueDeltas(NumIssueDeltas) {
|
||||
}
|
||||
|
||||
void MachineSchedInfo::initializeResources() {
|
||||
assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
|
||||
&& "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
|
||||
|
||||
// First, compute common resource usage info for each class because
|
||||
// most instructions will probably behave the same as their class.
|
||||
// Cannot allocate a vector of InstrRUsage so new each one.
|
||||
//
|
||||
vector<InstrRUsage> instrRUForClasses;
|
||||
instrRUForClasses.resize(numSchedClasses);
|
||||
for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
|
||||
// instrRUForClasses.push_back(new InstrRUsage);
|
||||
instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
|
||||
instrRUForClasses[sc] = classRUsages[sc];
|
||||
}
|
||||
|
||||
computeInstrResources(instrRUForClasses);
|
||||
computeIssueGaps(instrRUForClasses);
|
||||
}
|
||||
|
||||
|
||||
void MachineSchedInfo::computeInstrResources(
|
||||
const vector<InstrRUsage> &instrRUForClasses) {
|
||||
int numOpCodes = mii->getNumRealOpCodes();
|
||||
instrRUsages.resize(numOpCodes);
|
||||
|
||||
// First get the resource usage information from the class resource usages.
|
||||
for (MachineOpCode op = 0; op < numOpCodes; ++op) {
|
||||
InstrSchedClass sc = getSchedClass(op);
|
||||
assert(sc >= 0 && sc < numSchedClasses);
|
||||
instrRUsages[op] = instrRUForClasses[sc];
|
||||
}
|
||||
|
||||
// Now, modify the resource usages as specified in the deltas.
|
||||
for (unsigned i = 0; i < numUsageDeltas; ++i) {
|
||||
MachineOpCode op = usageDeltas[i].opCode;
|
||||
assert(op < numOpCodes);
|
||||
instrRUsages[op].addUsageDelta(usageDeltas[i]);
|
||||
}
|
||||
|
||||
// Then modify the issue restrictions as specified in the deltas.
|
||||
for (unsigned i = 0; i < numIssueDeltas; ++i) {
|
||||
MachineOpCode op = issueDeltas[i].opCode;
|
||||
assert(op < numOpCodes);
|
||||
instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void MachineSchedInfo::computeIssueGaps(
|
||||
const vector<InstrRUsage> &instrRUForClasses) {
|
||||
int numOpCodes = mii->getNumRealOpCodes();
|
||||
instrRUsages.resize(numOpCodes);
|
||||
|
||||
assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
|
||||
&& "numOpCodes invalid for implementation of class OpCodePair!");
|
||||
|
||||
// First, compute issue gaps between pairs of classes based on common
|
||||
// resources usages for each class, because most instruction pairs will
|
||||
// usually behave the same as their class.
|
||||
//
|
||||
int classPairGaps[numSchedClasses][numSchedClasses];
|
||||
for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
|
||||
for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
|
||||
int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
|
||||
instrRUForClasses[toSC]);
|
||||
classPairGaps[fromSC][toSC] = classPairGap;
|
||||
}
|
||||
|
||||
// Now, for each pair of instructions, use the class pair gap if both
|
||||
// instructions have identical resource usage as their respective classes.
|
||||
// If not, recompute the gap for the pair from scratch.
|
||||
|
||||
longestIssueConflict = 0;
|
||||
|
||||
for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
|
||||
for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
|
||||
int instrPairGap =
|
||||
(instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
|
||||
? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
|
||||
: ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
|
||||
|
||||
if (instrPairGap > 0) {
|
||||
issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
|
||||
conflictLists[fromOp].push_back(toOp);
|
||||
longestIssueConflict = max(longestIssueConflict, instrPairGap);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue