forked from OSchip/llvm-project
Optimized FMA intrinsic + FNEG , like
-(a*b+c) and FNEG + FMA, like a*b-c or (-a)*b+c. The bug description is here : https://llvm.org/bugs/show_bug.cgi?id=28892 Differential revision: https://reviews.llvm.org/D23313 llvm-svn: 280368
This commit is contained in:
Elena Demikhovsky
parent
29afb1937b
commit
4d7738dfde
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@ -4866,23 +4866,23 @@ static bool getTargetShuffleMaskIndices(SDValue MaskNode,
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return true;
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}
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static const Constant *getTargetShuffleMaskConstant(SDValue MaskNode) {
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MaskNode = peekThroughBitcasts(MaskNode);
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static const Constant *getTargetConstantFromNode(SDValue Op) {
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Op = peekThroughBitcasts(Op);
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auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
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if (!MaskLoad)
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auto *Load = dyn_cast<LoadSDNode>(Op);
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if (!Load)
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return nullptr;
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SDValue Ptr = MaskLoad->getBasePtr();
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SDValue Ptr = Load->getBasePtr();
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if (Ptr->getOpcode() == X86ISD::Wrapper ||
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Ptr->getOpcode() == X86ISD::WrapperRIP)
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Ptr = Ptr->getOperand(0);
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auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
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if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
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auto *CNode = dyn_cast<ConstantPoolSDNode>(Ptr);
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if (!CNode || CNode->isMachineConstantPoolEntry())
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return nullptr;
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return dyn_cast<Constant>(MaskCP->getConstVal());
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return dyn_cast<Constant>(CNode->getConstVal());
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}
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/// Calculates the shuffle mask corresponding to the target-specific opcode.
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@ -4992,7 +4992,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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DecodeVPERMILPMask(VT, RawMask, Mask);
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break;
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}
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodeVPERMILPMask(C, MaskEltSize, Mask);
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break;
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}
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@ -5006,7 +5006,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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DecodePSHUFBMask(RawMask, Mask);
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break;
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}
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodePSHUFBMask(C, Mask);
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break;
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}
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@ -5055,7 +5055,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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DecodeVPERMIL2PMask(VT, CtrlImm, RawMask, Mask);
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break;
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}
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodeVPERMIL2PMask(C, CtrlImm, MaskEltSize, Mask);
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break;
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}
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@ -5070,7 +5070,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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DecodeVPPERMMask(RawMask, Mask);
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break;
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}
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodeVPPERMMask(C, Mask);
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break;
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}
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@ -5087,7 +5087,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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DecodeVPERMVMask(RawMask, Mask);
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break;
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}
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodeVPERMVMask(C, VT, Mask);
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break;
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}
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@ -5099,7 +5099,7 @@ static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
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Ops.push_back(N->getOperand(0));
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Ops.push_back(N->getOperand(2));
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SDValue MaskNode = N->getOperand(1);
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if (auto *C = getTargetShuffleMaskConstant(MaskNode)) {
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if (auto *C = getTargetConstantFromNode(MaskNode)) {
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DecodeVPERMV3Mask(C, VT, Mask);
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break;
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}
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@ -30358,6 +30358,18 @@ static SDValue combineFneg(SDNode *N, SelectionDAG &DAG,
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case X86ISD::FNMSUB:
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return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
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Arg.getOperand(1), Arg.getOperand(2));
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case X86ISD::FMADD_RND:
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return DAG.getNode(X86ISD::FNMSUB_RND, DL, VT, Arg.getOperand(0),
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Arg.getOperand(1), Arg.getOperand(2), Arg.getOperand(3));
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case X86ISD::FMSUB_RND:
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return DAG.getNode(X86ISD::FNMADD_RND, DL, VT, Arg.getOperand(0),
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Arg.getOperand(1), Arg.getOperand(2), Arg.getOperand(3));
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case X86ISD::FNMADD_RND:
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return DAG.getNode(X86ISD::FMSUB_RND, DL, VT, Arg.getOperand(0),
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Arg.getOperand(1), Arg.getOperand(2), Arg.getOperand(3));
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case X86ISD::FNMSUB_RND:
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return DAG.getNode(X86ISD::FMADD_RND, DL, VT, Arg.getOperand(0),
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Arg.getOperand(1), Arg.getOperand(2), Arg.getOperand(3));
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}
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}
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return SDValue();
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@ -30386,6 +30398,45 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
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}
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return SDValue();
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}
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/// Returns true if the node \p N is FNEG(x) or FXOR (x, 0x80000000).
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bool isFNEG(const SDNode *N) {
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if (N->getOpcode() == ISD::FNEG)
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return true;
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if (N->getOpcode() == X86ISD::FXOR) {
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unsigned EltBits = N->getSimpleValueType(0).getScalarSizeInBits();
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SDValue Op1 = N->getOperand(1);
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auto isSignBitValue = [&](const ConstantFP *C) {
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return C->getValueAPF().bitcastToAPInt() == APInt::getSignBit(EltBits);
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};
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// There is more than one way to represent the same constant on
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// the different X86 targets. The type of the node may also depend on size.
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// - load scalar value and broadcast
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// - BUILD_VECTOR node
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// - load from a constant pool.
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// We check all variants here.
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if (Op1.getOpcode() == X86ISD::VBROADCAST) {
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if (auto *C = getTargetConstantFromNode(Op1.getOperand(0)))
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return isSignBitValue(cast<ConstantFP>(C));
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} else if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1)) {
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if (ConstantFPSDNode *CN = BV->getConstantFPSplatNode())
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return isSignBitValue(CN->getConstantFPValue());
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} else if (auto *C = getTargetConstantFromNode(Op1)) {
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if (C->getType()->isVectorTy()) {
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if (auto *SplatV = C->getSplatValue())
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return isSignBitValue(cast<ConstantFP>(SplatV));
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} else if (auto *FPConst = dyn_cast<ConstantFP>(C))
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return isSignBitValue(FPConst);
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}
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}
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return false;
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}
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/// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
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static SDValue combineFOr(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget &Subtarget) {
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@ -30401,6 +30452,9 @@ static SDValue combineFOr(SDNode *N, SelectionDAG &DAG,
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if (C->getValueAPF().isPosZero())
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return N->getOperand(0);
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if (isFNEG(N))
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if (SDValue NewVal = combineFneg(N, DAG, Subtarget))
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return NewVal;
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return lowerX86FPLogicOp(N, DAG, Subtarget);
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}
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@ -30810,9 +30864,9 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
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SDValue B = N->getOperand(1);
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SDValue C = N->getOperand(2);
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bool NegA = (A.getOpcode() == ISD::FNEG);
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bool NegB = (B.getOpcode() == ISD::FNEG);
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bool NegC = (C.getOpcode() == ISD::FNEG);
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bool NegA = isFNEG(A.getNode());
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bool NegB = isFNEG(B.getNode());
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bool NegC = isFNEG(C.getNode());
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// Negative multiplication when NegA xor NegB
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bool NegMul = (NegA != NegB);
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@ -30823,13 +30877,22 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
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if (NegC)
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C = C.getOperand(0);
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unsigned Opcode;
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unsigned NewOpcode;
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if (!NegMul)
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Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
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NewOpcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
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else
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Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
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NewOpcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
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return DAG.getNode(Opcode, dl, VT, A, B, C);
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if (N->getOpcode() == X86ISD::FMADD_RND) {
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switch (NewOpcode) {
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case X86ISD::FMADD: NewOpcode = X86ISD::FMADD_RND; break;
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case X86ISD::FMSUB: NewOpcode = X86ISD::FMSUB_RND; break;
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case X86ISD::FNMADD: NewOpcode = X86ISD::FNMADD_RND; break;
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case X86ISD::FNMSUB: NewOpcode = X86ISD::FNMSUB_RND; break;
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}
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return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3));
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}
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return DAG.getNode(NewOpcode, dl, VT, A, B, C);
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}
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static SDValue combineZext(SDNode *N, SelectionDAG &DAG,
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@ -31559,6 +31622,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::VPERM2X128:
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case X86ISD::VZEXT_MOVL:
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case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);
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case X86ISD::FMADD:
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case X86ISD::FMADD_RND:
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case ISD::FMA: return combineFMA(N, DAG, Subtarget);
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case ISD::MGATHER:
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case ISD::MSCATTER: return combineGatherScatter(N, DAG);
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@ -0,0 +1,86 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 -mattr=+fma | FileCheck %s
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; This test checks combinations of FNEG and FMA intrinsics
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define <8 x float> @test1(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%sub.i = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
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%0 = tail call <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %sub.i) #2
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ret <8 x float> %0
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}
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declare <8 x float> @llvm.x86.fma.vfmadd.ps.256(<8 x float>, <8 x float>, <8 x float>)
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfnmsub213ps %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %a, <4 x float> %b, <4 x float> %c) #2
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%sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %0
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ret <4 x float> %sub.i
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}
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declare <4 x float> @llvm.x86.fma.vfmadd.ps(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfnmadd213ss %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %xmm1
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; CHECK-NEXT: vxorps %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float> %a, <4 x float> %b, <4 x float> %c) #2
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%sub.i = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %0
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ret <4 x float> %sub.i
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}
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declare <4 x float> @llvm.x86.fma.vfnmadd.ss(<4 x float> %a, <4 x float> %b, <4 x float> %c)
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define <8 x float> @test4(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c) #2
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%sub.i = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %0
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ret <8 x float> %sub.i
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}
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define <8 x float> @test5(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %ymm3
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; CHECK-NEXT: vxorps %ymm3, %ymm2, %ymm2
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; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0
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; CHECK-NEXT: retq
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entry:
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%sub.c = fsub <8 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
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%0 = tail call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %sub.c) #2
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ret <8 x float> %0
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}
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declare <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>)
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define <2 x double> @test6(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfnmsub213pd %xmm2, %xmm1, %xmm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double> %a, <2 x double> %b, <2 x double> %c) #2
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%sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %0
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ret <2 x double> %sub.i
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}
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declare <2 x double> @llvm.x86.fma.vfmadd.pd(<2 x double> %a, <2 x double> %b, <2 x double> %c)
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@ -7,8 +7,7 @@
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define <16 x float> @test1(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm2, %zmm2
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; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: vfmsub213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%sub.i = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
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@ -24,8 +23,7 @@ declare <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float>, <16 x fl
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define <16 x float> @test2(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <16 x float> @llvm.x86.avx512.mask.vfmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 -1, i32 4) #2
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@ -36,8 +34,7 @@ entry:
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define <16 x float> @test3(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: vfnmadd213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK-NEXT: vfmsub213ps %zmm2, %zmm1, %zmm0
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; CHECK-NEXT: retq
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entry:
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%0 = tail call <16 x float> @llvm.x86.avx512.mask.vfnmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 -1, i32 4) #2
|
||||
|
|
@ -48,8 +45,7 @@ entry:
|
|||
define <16 x float> @test4(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
|
||||
; CHECK-LABEL: test4:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfnmsub213ps %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vfmadd213ps %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 -1, i32 4) #2
|
||||
|
|
@ -60,8 +56,7 @@ entry:
|
|||
define <16 x float> @test5(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
|
||||
; CHECK-LABEL: test5:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm2, %zmm2
|
||||
; CHECK-NEXT: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: vfmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%sub.i = fsub <16 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c
|
||||
|
|
@ -72,8 +67,7 @@ entry:
|
|||
define <16 x float> @test6(<16 x float> %a, <16 x float> %b, <16 x float> %c) {
|
||||
; CHECK-LABEL: test6:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfnmsub213ps {ru-sae}, %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: vxorps {{.*}}(%rip){1to16}, %zmm0, %zmm0
|
||||
; CHECK-NEXT: vfmadd213ps {ru-sae}, %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <16 x float> @llvm.x86.avx512.mask.vfnmsub.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 -1, i32 2) #2
|
||||
|
|
@ -85,8 +79,7 @@ entry:
|
|||
define <8 x float> @test7(<8 x float> %a, <8 x float> %b, <8 x float> %c) {
|
||||
; CHECK-LABEL: test7:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfmsub213ps %ymm2, %ymm1, %ymm0
|
||||
; CHECK-NEXT: vxorps {{.*}}(%rip){1to8}, %ymm0, %ymm0
|
||||
; CHECK-NEXT: vfnmadd213ps %ymm2, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float> %a, <8 x float> %b, <8 x float> %c) #2
|
||||
|
|
@ -108,3 +101,44 @@ entry:
|
|||
|
||||
declare <8 x float> @llvm.x86.fma.vfmsub.ps.256(<8 x float>, <8 x float>, <8 x float>)
|
||||
|
||||
|
||||
define <8 x double> @test9(<8 x double> %a, <8 x double> %b, <8 x double> %c) {
|
||||
; CHECK-LABEL: test9:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfnmsub213pd %zmm2, %zmm1, %zmm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8 -1, i32 4) #2
|
||||
%sub.i = fsub <8 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %0
|
||||
ret <8 x double> %sub.i
|
||||
}
|
||||
|
||||
declare <8 x double> @llvm.x86.avx512.mask.vfmadd.pd.512(<8 x double> %a, <8 x double> %b, <8 x double> %c, i8, i32)
|
||||
|
||||
define <4 x double> @test10(<4 x double> %a, <4 x double> %b, <4 x double> %c) {
|
||||
; CHECK-LABEL: test10:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfnmsub213pd %ymm2, %ymm1, %ymm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8 -1) #2
|
||||
%sub.i = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, double -0.000000e+00>, %0
|
||||
ret <4 x double> %sub.i
|
||||
}
|
||||
|
||||
declare <4 x double> @llvm.x86.avx512.mask.vfmadd.pd.256(<4 x double> %a, <4 x double> %b, <4 x double> %c, i8)
|
||||
|
||||
define <2 x double> @test11(<2 x double> %a, <2 x double> %b, <2 x double> %c) {
|
||||
; CHECK-LABEL: test11:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: vfnmsub213sd %xmm2, %xmm0, %xmm1
|
||||
; CHECK-NEXT: vmovaps %xmm1, %xmm0
|
||||
; CHECK-NEXT: retq
|
||||
entry:
|
||||
%0 = tail call <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 -1, i32 4) #2
|
||||
%sub.i = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %0
|
||||
ret <2 x double> %sub.i
|
||||
}
|
||||
|
||||
declare <2 x double> @llvm.x86.avx512.mask.vfmadd.sd(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8, i32)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue