forked from OSchip/llvm-project
AMDGPU: Implement isFPExtFoldable
This helps match v_mad_mix* in some cases. llvm-svn: 315744
This commit is contained in:
Matt Arsenault
parent
28b3aa3663
commit
4d70754e3c
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@ -827,6 +827,17 @@ bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
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return isZExtFree(Val.getValueType(), VT2);
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}
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// v_mad_mix* support a conversion from f16 to f32.
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//
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// There is only one special case when denormals are enabled we don't currently,
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// where this is OK to use.
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bool AMDGPUTargetLowering::isFPExtFoldable(unsigned Opcode,
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EVT DestVT, EVT SrcVT) const {
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return Opcode == ISD::FMAD && Subtarget->hasMadMixInsts() &&
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DestVT.getScalarType() == MVT::f32 && !Subtarget->hasFP32Denormals() &&
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SrcVT.getScalarType() == MVT::f16;
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}
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bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
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// There aren't really 64-bit registers, but pairs of 32-bit ones and only a
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// limited number of native 64-bit operations. Shrinking an operation to fit
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@ -143,6 +143,7 @@ public:
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bool isZExtFree(Type *Src, Type *Dest) const override;
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bool isZExtFree(EVT Src, EVT Dest) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const override;
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bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
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@ -0,0 +1,388 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32FLUSH %s
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,GFX9,GFX9-F32DENORM %s
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; RUN: llc -march=amdgcn -mcpu=gfx803 -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32FLUSH %s
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; RUN: llc -march=amdgcn -mcpu=gfx803 -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX89,VI,VI-F32DENORM %s
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; fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
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; GCN-LABEL: {{^}}fadd_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16
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; GFX9-F32DENORM-NEXT: v_add_f32
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define float @fadd_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
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entry:
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%mul = fmul half %x, %y
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%mul.ext = fpext half %mul to float
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%add = fadd float %mul.ext, %z
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ret float %add
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}
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; f16->f64 is not free.
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; GCN-LABEL: {{^}}fadd_fpext_fmul_f16_to_f64:
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; GFX89: v_mul_f16
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; GFX89: v_cvt_f32_f16
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; GFX89: v_cvt_f64_f32
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; GFX89: v_add_f64
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define double @fadd_fpext_fmul_f16_to_f64(half %x, half %y, double %z) #0 {
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entry:
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%mul = fmul half %x, %y
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%mul.ext = fpext half %mul to double
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%add = fadd double %mul.ext, %z
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ret double %add
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}
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; f32->f64 is not free.
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; GCN-LABEL: {{^}}fadd_fpext_fmul_f32_to_f64:
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; GCN: v_mul_f32
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; GCN: v_cvt_f64_f32
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; GCN: v_add_f64
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define double @fadd_fpext_fmul_f32_to_f64(float %x, float %y, double %z) #0 {
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entry:
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%mul = fmul float %x, %y
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%mul.ext = fpext float %mul to double
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%add = fadd double %mul.ext, %z
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ret double %add
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}
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; fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x)
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; GCN-LABEL: {{^}}fadd_fpext_fmul_f16_to_f32_commute:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v0, v1, v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16
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; GFX9-F32DENORM-NEXT: v_add_f32
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fadd_fpext_fmul_f16_to_f32_commute(half %x, half %y, float %z) #0 {
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entry:
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%mul = fmul half %x, %y
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%mul.ext = fpext half %mul to float
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%add = fadd float %z, %mul.ext
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ret float %add
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}
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; fold (fadd (fma x, y, (fpext (fmul u, v))), z)
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; -> (fma x, y, (fma (fpext u), (fpext v), z))
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; GCN-LABEL: {{^}}fadd_muladd_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v2, v2, v3, v4 op_sel_hi:[1,1,0]
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; GFX9-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1
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; GFX9-F32FLUSH-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16
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; GFX9-F32DENORM-NEXT: v_fma_f32
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; GFX9-F32DENORM-NEXT: v_add_f32
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fadd_muladd_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
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entry:
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%mul = fmul half %u, %v
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%mul.ext = fpext half %mul to float
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%fma = call float @llvm.fmuladd.f32(float %x, float %y, float %mul.ext)
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%add = fadd float %fma, %z
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ret float %add
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}
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; fold (fadd x, (fma y, z, (fpext (fmul u, v)))
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; -> (fma y, z, (fma (fpext u), (fpext v), x))
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; GCN-LABEL: {{^}}fadd_muladd_fpext_fmul_f16_to_f32_commute:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v2, v2, v3, v4 op_sel_hi:[1,1,0]
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; GFX9-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1
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; GFX9-F32FLUSH-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16
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; GFX9-F32DENORM-NEXT: v_fma_f32
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; GFX9-F32DENORM-NEXT: v_add_f32
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fadd_muladd_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u, half %v, float %z) #0 {
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entry:
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%mul = fmul half %u, %v
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%mul.ext = fpext half %mul to float
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%fma = call float @llvm.fmuladd.f32(float %x, float %y, float %mul.ext)
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%add = fadd float %z, %fma
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ret float %add
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}
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; GCN-LABEL: {{^}}fadd_fmad_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v2, v2, v3, v4 op_sel_hi:[1,1,0]
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; GFX9-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1
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; GFX9-F32FLUSH-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v2, v2, v3
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v2, v2
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; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v2
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define float @fadd_fmad_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
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entry:
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%mul = fmul half %u, %v
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%mul.ext = fpext half %mul to float
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%mul1 = fmul contract float %x, %y
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%fmad = fadd contract float %mul1, %mul.ext
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%add = fadd float %fmad, %z
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ret float %add
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}
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; fold (fadd (fma x, y, (fpext (fmul u, v))), z)
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; -> (fma x, y, (fma (fpext u), (fpext v), z))
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; GCN-LABEL: {{^}}fadd_fma_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX89: v_mul_f16
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; GFX89: v_cvt_f32_f16
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; GFX89: v_fma_f32
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; GFX89: v_add_f32
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define float @fadd_fma_fpext_fmul_f16_to_f32(float %x, float %y, half %u, half %v, float %z) #0 {
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entry:
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%mul = fmul contract half %u, %v
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%mul.ext = fpext half %mul to float
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%fma = call float @llvm.fma.f32(float %x, float %y, float %mul.ext)
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%add = fadd float %fma, %z
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ret float %add
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}
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; GCN-LABEL: {{^}}fadd_fma_fpext_fmul_f16_to_f32_commute:
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; GCN: s_waitcnt
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; GFX89: v_mul_f16
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; GFX89: v_cvt_f32_f16
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; GFX89: v_fma_f32
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; GFX89: v_add_f32
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define float @fadd_fma_fpext_fmul_f16_to_f32_commute(float %x, float %y, half %u, half %v, float %z) #0 {
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entry:
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%mul = fmul contract half %u, %v
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%mul.ext = fpext half %mul to float
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%fma = call float @llvm.fma.f32(float %x, float %y, float %mul.ext)
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%add = fadd float %z, %fma
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ret float %add
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}
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; fold (fadd x, (fpext (fma y, z, (fmul u, v)))
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; -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))
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; GCN-LABEL: {{^}}fadd_fpext_fmuladd_f16_to_f32:
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; GFX9: v_mul_f16
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; GFX9: v_fma_legacy_f16
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; GFX9: v_cvt_f32_f16
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; GFX9: v_add_f32_e32
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define float @fadd_fpext_fmuladd_f16_to_f32(float %x, half %y, half %z, half %u, half %v) #0 {
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entry:
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%mul = fmul contract half %u, %v
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%fma = call half @llvm.fmuladd.f16(half %y, half %z, half %mul)
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%ext.fma = fpext half %fma to float
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%add = fadd float %x, %ext.fma
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ret float %add
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}
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; GCN-LABEL: {{^}}fadd_fpext_fma_f16_to_f32:
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; GFX9: v_mul_f16
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; GFX9: v_fma_legacy_f16
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; GFX9: v_cvt_f32_f16
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; GFX9: v_add_f32_e32
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define float @fadd_fpext_fma_f16_to_f32(float %x, half %y, half %z, half %u, half %v) #0 {
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entry:
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%mul = fmul contract half %u, %v
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%fma = call half @llvm.fma.f16(half %y, half %z, half %mul)
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%ext.fma = fpext half %fma to float
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%add = fadd float %x, %ext.fma
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ret float %add
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}
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; GCN-LABEL: {{^}}fadd_fpext_fma_f16_to_f32_commute:
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; GFX9: v_mul_f16
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; GFX9: v_fma_legacy_f16
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; GFX9: v_cvt_f32_f16
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; GFX9: v_add_f32_e32
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define float @fadd_fpext_fma_f16_to_f32_commute(float %x, half %y, half %z, half %u, half %v) #0 {
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entry:
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%mul = fmul contract half %u, %v
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%fma = call half @llvm.fma.f16(half %y, half %z, half %mul)
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%ext.fma = fpext half %fma to float
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%add = fadd float %ext.fma, %x
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ret float %add
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}
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; fold (fsub (fpext (fmul x, y)), z)
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; -> (fma (fpext x), (fpext y), (fneg z))
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; GCN-LABEL: {{^}}fsub_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v0, v0, v1
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fsub_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
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entry:
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%mul = fmul half %x, %y
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%mul.ext = fpext half %mul to float
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%add = fsub float %mul.ext, %z
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ret float %add
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}
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; fold (fsub x, (fpext (fmul y, z)))
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; -> (fma (fneg (fpext y)), (fpext z), x)
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; GCN-LABEL: {{^}}fsub_fpext_fmul_f16_to_f32_commute:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, -v1, v2, v0 op_sel_hi:[1,1,0]
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16_e32
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32
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; GFX9-F32DENORM-NEXT: v_sub_f32_e32
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fsub_fpext_fmul_f16_to_f32_commute(float %x, half %y, half %z) #0 {
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entry:
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%mul = fmul contract half %y, %z
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%mul.ext = fpext half %mul to float
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%add = fsub contract float %x, %mul.ext
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ret float %add
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}
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; fold (fsub (fpext (fneg (fmul, x, y))), z)
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; -> (fneg (fma (fpext x), (fpext y), z))
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; FIXME: Should be able to fold fneg
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; GCN-LABEL: {{^}}fsub_fpext_fneg_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_xor_b32_e32 v1, 0x8000, v1
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16_e64 v0, v0, -v1
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fsub_fpext_fneg_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
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entry:
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%mul = fmul half %x, %y
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%neg.mul = fsub half -0.0, %mul
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%neg.mul.ext = fpext half %neg.mul to float
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%add = fsub float %neg.mul.ext, %z
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ret float %add
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}
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; fold (fsub (fneg (fpext (fmul, x, y))), z)
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; -> (fneg (fma (fpext x)), (fpext y), z)
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; FIXME: Should be able to fold fneg
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; GCN-LABEL: {{^}}fsub_fneg_fpext_fmul_f16_to_f32:
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; GCN: s_waitcnt
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; GFX9-F32FLUSH-NEXT: v_xor_b32_e32 v1, 0x8000, v1
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; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, v0, v1, -v2 op_sel_hi:[1,1,0]{{$}}
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; GFX9-F32FLUSH-NEXT: s_setpc_b64
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; GFX9-F32DENORM-NEXT: v_mul_f16_e64 v0, v0, -v1
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; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2
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; GFX9-F32DENORM-NEXT: s_setpc_b64
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define float @fsub_fneg_fpext_fmul_f16_to_f32(half %x, half %y, float %z) #0 {
|
||||
entry:
|
||||
%mul = fmul half %x, %y
|
||||
%mul.ext = fpext half %mul to float
|
||||
%neg.mul.ext = fsub float -0.0, %mul.ext
|
||||
%add = fsub float %neg.mul.ext, %z
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; fold (fsub (fmad x, y, (fpext (fmul u, v))), z)
|
||||
; -> (fmad x, y (fmad (fpext u), (fpext v), (fneg z)))
|
||||
; GCN-LABEL: {{^}}fsub_muladd_fpext_mul_f16_to_f32:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v2, v3, v4, -v2 op_sel_hi:[1,1,0]{{$}}
|
||||
; GFX9-F32FLUSH-NEXT: v_mac_f32_e32 v2, v0, v1
|
||||
; GFX9-F32FLUSH-NEXT: v_mov_b32_e32 v0, v2
|
||||
; GFX9-F32FLUSH-NEXT: s_setpc_b64
|
||||
|
||||
; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
|
||||
; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; GFX9-F32DENORM-NEXT: v_fma_f32 v0, v0, v1, v3
|
||||
; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v2
|
||||
; GFX9-F32DENORM-NEXT: s_setpc_b64
|
||||
define float @fsub_muladd_fpext_mul_f16_to_f32(float %x, float %y, float %z, half %u, half %v) #0 {
|
||||
entry:
|
||||
%mul = fmul half %u, %v
|
||||
%mul.ext = fpext half %mul to float
|
||||
%fma = call float @llvm.fmuladd.f32(float %x, float %y, float %mul.ext)
|
||||
%add = fsub float %fma, %z
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; fold (fsub (fpext (fmad x, y, (fmul u, v))), z)
|
||||
; -> (fmad (fpext x), (fpext y),
|
||||
; (fmad (fpext u), (fpext v), (fneg z)))
|
||||
|
||||
; GCN-LABEL: {{^}}fsub_fpext_muladd_mul_f16_to_f32:
|
||||
; GFX9: v_mul_f16
|
||||
; GFX9: v_fma_legacy_f16
|
||||
; GFX9: v_cvt_f32_f16
|
||||
; GFX9: v_sub_f32
|
||||
; GCN: s_setpc_b64
|
||||
define float @fsub_fpext_muladd_mul_f16_to_f32(half %x, half %y, float %z, half %u, half %v) #0 {
|
||||
entry:
|
||||
%mul = fmul half %u, %v
|
||||
%fma = call half @llvm.fmuladd.f16(half %x, half %y, half %mul)
|
||||
%fma.ext = fpext half %fma to float
|
||||
%add = fsub float %fma.ext, %z
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; fold (fsub x, (fmad y, z, (fpext (fmul u, v))))
|
||||
; -> (fmad (fneg y), z, (fmad (fneg (fpext u)), (fpext v), x))
|
||||
; GCN-LABEL: {{^}}fsub_muladd_fpext_mul_f16_to_f32_commute:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-F32FLUSH-NEXT: v_mad_mix_f32 v0, -v3, v4, v0 op_sel_hi:[1,1,0]{{$}}
|
||||
; GFX9-F32FLUSH-NEXT: v_mad_f32 v0, -v1, v2, v0{{$}}
|
||||
; GFX9-F32FLUSH-NEXT: s_setpc_b64
|
||||
|
||||
; GFX9-F32DENORM-NEXT: v_mul_f16_e32 v3, v3, v4
|
||||
; GFX9-F32DENORM-NEXT: v_cvt_f32_f16_e32 v3, v3
|
||||
; GFX9-F32DENORM-NEXT: v_fma_f32 v1, v1, v2, v3
|
||||
; GFX9-F32DENORM-NEXT: v_sub_f32_e32 v0, v0, v1
|
||||
; GFX9-F32DENORM-NEXT: s_setpc_b64
|
||||
define float @fsub_muladd_fpext_mul_f16_to_f32_commute(float %x, float %y, float %z, half %u, half %v) #0 {
|
||||
entry:
|
||||
%mul = fmul half %u, %v
|
||||
%mul.ext = fpext half %mul to float
|
||||
%fma = call float @llvm.fmuladd.f32(float %y, float %z, float %mul.ext)
|
||||
%add = fsub float %x, %fma
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; fold (fsub x, (fpext (fma y, z, (fmul u, v))))
|
||||
; -> (fma (fneg (fpext y)), (fpext z),
|
||||
; (fma (fneg (fpext u)), (fpext v), x))
|
||||
; GCN-LABEL: {{^}}fsub_fpext_muladd_mul_f16_to_f32_commute:
|
||||
; GCN: s_waitcnt
|
||||
; GFX9-NEXT: v_mul_f16_e32 v3, v3, v4
|
||||
; GFX9-NEXT: v_fma_legacy_f16 v1, v1, v2, v3
|
||||
; GFX9-NEXT: v_cvt_f32_f16_e32 v1, v1
|
||||
; GFX9-NEXT: v_sub_f32_e32 v0, v0, v1
|
||||
; GFX9-NEXT: s_setpc_b64
|
||||
define float @fsub_fpext_muladd_mul_f16_to_f32_commute(float %x, half %y, half %z, half %u, half %v) #0 {
|
||||
entry:
|
||||
%mul = fmul half %u, %v
|
||||
%fma = call half @llvm.fmuladd.f16(half %y, half %z, half %mul)
|
||||
%fma.ext = fpext half %fma to float
|
||||
%add = fsub float %x, %fma.ext
|
||||
ret float %add
|
||||
}
|
||||
|
||||
declare float @llvm.fmuladd.f32(float, float, float) #0
|
||||
declare float @llvm.fma.f32(float, float, float) #0
|
||||
declare half @llvm.fmuladd.f16(half, half, half) #0
|
||||
declare half @llvm.fma.f16(half, half, half) #0
|
||||
|
||||
attributes #0 = { nounwind readnone speculatable }
|
||||
Loading…
Reference in New Issue