forked from OSchip/llvm-project
parent
e8863b8f00
commit
4d64f96530
|
@ -1811,8 +1811,7 @@ FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg,
|
|||
TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
|
||||
};
|
||||
std::vector<unsigned> Consts;
|
||||
for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
|
||||
int OtherSrcIdx = SrcIndices[i];
|
||||
for (int OtherSrcIdx : SrcIndices) {
|
||||
int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
|
||||
if (OtherSrcIdx < 0 || OtherSelIdx < 0)
|
||||
continue;
|
||||
|
|
|
@ -71,10 +71,9 @@ const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
|
|||
&AMDGPU::SReg_256RegClass
|
||||
};
|
||||
|
||||
for (unsigned i = 0, e = sizeof(BaseClasses) /
|
||||
sizeof(const TargetRegisterClass*); i != e; ++i) {
|
||||
if (BaseClasses[i]->contains(Reg)) {
|
||||
return BaseClasses[i];
|
||||
for (const TargetRegisterClass *BaseClass : BaseClasses) {
|
||||
if (BaseClass->contains(Reg)) {
|
||||
return BaseClass;
|
||||
}
|
||||
}
|
||||
return nullptr;
|
||||
|
|
Loading…
Reference in New Issue