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[MC][RISCV] Set UseIntegratedAssembler to true 

to align with most other targets. Also, -fintegrated-as is the default
for clang -target riscv*.
This commit is contained in:
Fangrui Song 2020-07-12 21:04:31 -07:00
parent 78443666bc
commit 4d5fd0ee5e
5 changed files with 10 additions and 7 deletions
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1
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
View File

@ -27,7 +27,6 @@ RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) {
ExceptionsType = ExceptionHandling::DwarfCFI;
Data16bitsDirective = "\t.half\t";
Data32bitsDirective = "\t.word\t";
UseIntegratedAssembler = false;
}
const MCExpr *RISCVMCAsmInfo::getExprForFDESymbol(const MCSymbol *Sym,

4
llvm/test/CodeGen/RISCV/branch-relaxation.ll
View File

@ -11,7 +11,7 @@ define void @relax_bcc(i1 %a) nounwind {
; CHECK-NEXT: j .LBB0_2
; CHECK-NEXT: .LBB0_1: # %iftrue
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 4096
; CHECK-NEXT: .zero 4096
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: .LBB0_2: # %tail
; CHECK-NEXT: ret
@ -38,7 +38,7 @@ define i32 @relax_jal(i1 %a) nounwind {
; CHECK-NEXT: #APP
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: .space 1048576
; CHECK-NEXT: .zero 1048576
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: addi a0, zero, 1
; CHECK-NEXT: ret

4
llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; These test that we can use both the architectural names (x*) and the ABI names

4
llvm/test/CodeGen/RISCV/inline-asm.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -no-integrated-as < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
@gi = external global i32

4
llvm/test/CodeGen/RISCV/large-stack.ll
View File

@ -64,10 +64,12 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-NEXT: add a1, a2, a1
; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-EMPTY:
; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: sw a0, 0(a1)
; RV32I-FPELIM-NEXT: #APP
; RV32I-FPELIM-NEXT: nop
; RV32I-FPELIM-EMPTY:
; RV32I-FPELIM-NEXT: #NO_APP
; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672
@ -103,10 +105,12 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-WITHFP-NEXT: add a1, a2, a1
; RV32I-WITHFP-NEXT: #APP
; RV32I-WITHFP-NEXT: nop
; RV32I-WITHFP-EMPTY:
; RV32I-WITHFP-NEXT: #NO_APP
; RV32I-WITHFP-NEXT: sw a0, 0(a1)
; RV32I-WITHFP-NEXT: #APP
; RV32I-WITHFP-NEXT: nop
; RV32I-WITHFP-EMPTY:
; RV32I-WITHFP-NEXT: #NO_APP
; RV32I-WITHFP-NEXT: lui a0, 97
; RV32I-WITHFP-NEXT: addi a0, a0, 688