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[RISCV] Merge FMulAdd and FMulSub scheduler classes to a single FMA scheduler class. NFC 

It's unlikely that FMADD and FMSUB would have different scheduling
information so merge them.

Reviewed By: HsiangKai

Differential Revision: https://reviews.llvm.org/D99140
This commit is contained in:
Craig Topper 2021-03-26 16:37:15 -07:00
parent 12ac0403b1
commit 4d5ee71b52
6 changed files with 30 additions and 48 deletions
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8
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
View File

@ -82,16 +82,16 @@ def FSD : RVInstS<0b011, OPC_STORE_FP, (outs),
Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
def FMADD_D : FPFMAD_rrr_frm<OPC_MADD, "fmadd.d">,
Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FMADD_D, "fmadd.d">;
def FMSUB_D : FPFMAD_rrr_frm<OPC_MSUB, "fmsub.d">,
Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FMSUB_D, "fmsub.d">;
def FNMSUB_D : FPFMAD_rrr_frm<OPC_NMSUB, "fnmsub.d">,
Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FNMSUB_D, "fnmsub.d">;
def FNMADD_D : FPFMAD_rrr_frm<OPC_NMADD, "fnmadd.d">,
Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
Sched<[WriteFMA64, ReadFMA64, ReadFMA64, ReadFMA64]>;
def : FPFMADDynFrmAlias<FNMADD_D, "fnmadd.d">;
def FADD_D : FPALUD_rr_frm<0b0000001, "fadd.d">,

8
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
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@ -117,16 +117,16 @@ def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>;
def FMADD_S : FPFMAS_rrr_frm<OPC_MADD, "fmadd.s">,
Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FMADD_S, "fmadd.s">;
def FMSUB_S : FPFMAS_rrr_frm<OPC_MSUB, "fmsub.s">,
Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FMSUB_S, "fmsub.s">;
def FNMSUB_S : FPFMAS_rrr_frm<OPC_NMSUB, "fnmsub.s">,
Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FNMSUB_S, "fnmsub.s">;
def FNMADD_S : FPFMAS_rrr_frm<OPC_NMADD, "fnmadd.s">,
Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
Sched<[WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32]>;
def : FPFMASDynFrmAlias<FNMADD_S, "fnmadd.s">;
def FADD_S : FPALUS_rr_frm<0b0000000, "fadd.s">,

8
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
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@ -83,16 +83,16 @@ def FSH : RVInstS<0b001, OPC_STORE_FP, (outs),
Sched<[WriteFST16, ReadStoreData, ReadFMemBase]>;
def FMADD_H : FPFMAH_rrr_frm<OPC_MADD, "fmadd.h">,
Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>;
Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FMADD_H, "fmadd.h">;
def FMSUB_H : FPFMAH_rrr_frm<OPC_MSUB, "fmsub.h">,
Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>;
Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FMSUB_H, "fmsub.h">;
def FNMSUB_H : FPFMAH_rrr_frm<OPC_NMSUB, "fnmsub.h">,
Sched<[WriteFMulSub16, ReadFMulSub16, ReadFMulSub16, ReadFMulSub16]>;
Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FNMSUB_H, "fnmsub.h">;
def FNMADD_H : FPFMAH_rrr_frm<OPC_NMADD, "fnmadd.h">,
Sched<[WriteFMulAdd16, ReadFMulAdd16, ReadFMulAdd16, ReadFMulAdd16]>;
Sched<[WriteFMA16, ReadFMA16, ReadFMA16, ReadFMA16]>;
def : FPFMAHDynFrmAlias<FNMADD_H, "fnmadd.h">;
def FADD_H : FPALUH_rr_frm<0b0000010, "fadd.h">,

18
llvm/lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -145,14 +145,12 @@ def : WriteRes<WriteFMovI64ToF64, [RocketUnitFPALU]>;
// FP multiplication
let Latency = 5 in {
def : WriteRes<WriteFMul32, [RocketUnitFPALU]>;
def : WriteRes<WriteFMulAdd32, [RocketUnitFPALU]>;
def : WriteRes<WriteFMulSub32, [RocketUnitFPALU]>;
def : WriteRes<WriteFMA32, [RocketUnitFPALU]>;
}
let Latency = 7 in {
def : WriteRes<WriteFMul64, [RocketUnitFPALU]>;
def : WriteRes<WriteFMulAdd64, [RocketUnitFPALU]>;
def : WriteRes<WriteFMulSub64, [RocketUnitFPALU]>;
def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
}
// FP division
@ -203,11 +201,9 @@ def : ReadAdvance<ReadFMemBase, 0>;
def : ReadAdvance<ReadFALU32, 0>;
def : ReadAdvance<ReadFALU64, 0>;
def : ReadAdvance<ReadFMul32, 0>;
def : ReadAdvance<ReadFMulAdd32, 0>;
def : ReadAdvance<ReadFMulSub32, 0>;
def : ReadAdvance<ReadFMA32, 0>;
def : ReadAdvance<ReadFMul64, 0>;
def : ReadAdvance<ReadFMulAdd64, 0>;
def : ReadAdvance<ReadFMulSub64, 0>;
def : ReadAdvance<ReadFMA64, 0>;
def : ReadAdvance<ReadFDiv32, 0>;
def : ReadAdvance<ReadFDiv64, 0>;
def : ReadAdvance<ReadFSqrt32, 0>;
@ -250,9 +246,8 @@ def : WriteRes<WriteFCvtF16ToI32, []>;
def : WriteRes<WriteFDiv16, []>;
def : WriteRes<WriteFCmp16, []>;
def : WriteRes<WriteFLD16, []>;
def : WriteRes<WriteFMulAdd16, []>;
def : WriteRes<WriteFMA16, []>;
def : WriteRes<WriteFMinMax16, []>;
def : WriteRes<WriteFMulSub16, []>;
def : WriteRes<WriteFMul16, []>;
def : WriteRes<WriteFMovI16ToF16, []>;
def : WriteRes<WriteFMovF16ToI16, []>;
@ -272,9 +267,8 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
def : ReadAdvance<ReadFCvtF16ToI32, 0>;
def : ReadAdvance<ReadFDiv16, 0>;
def : ReadAdvance<ReadFCmp16, 0>;
def : ReadAdvance<ReadFMulAdd16, 0>;
def : ReadAdvance<ReadFMA16, 0>;
def : ReadAdvance<ReadFMinMax16, 0>;
def : ReadAdvance<ReadFMulSub16, 0>;
def : ReadAdvance<ReadFMul16, 0>;
def : ReadAdvance<ReadFMovI16ToF16, 0>;
def : ReadAdvance<ReadFMovF16ToI16, 0>;

18
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -103,8 +103,7 @@ def : WriteRes<WriteAtomicLDD, [SiFive7PipeA]>;
let Latency = 5 in {
def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
def : WriteRes<WriteFMulAdd32, [SiFive7PipeB]>;
def : WriteRes<WriteFMulSub32, [SiFive7PipeB]>;
def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
}
let Latency = 3 in {
def : WriteRes<WriteFSGNJ32, [SiFive7PipeB]>;
@ -120,8 +119,7 @@ def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
let Latency = 7 in {
def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
def : WriteRes<WriteFMulAdd64, [SiFive7PipeB]>;
def : WriteRes<WriteFMulSub64, [SiFive7PipeB]>;
def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
}
let Latency = 3 in {
def : WriteRes<WriteFSGNJ64, [SiFive7PipeB]>;
@ -191,11 +189,9 @@ def : ReadAdvance<ReadFMemBase, 0>;
def : ReadAdvance<ReadFALU32, 0>;
def : ReadAdvance<ReadFALU64, 0>;
def : ReadAdvance<ReadFMul32, 0>;
def : ReadAdvance<ReadFMulAdd32, 0>;
def : ReadAdvance<ReadFMulSub32, 0>;
def : ReadAdvance<ReadFMA32, 0>;
def : ReadAdvance<ReadFMul64, 0>;
def : ReadAdvance<ReadFMulAdd64, 0>;
def : ReadAdvance<ReadFMulSub64, 0>;
def : ReadAdvance<ReadFMA64, 0>;
def : ReadAdvance<ReadFDiv32, 0>;
def : ReadAdvance<ReadFDiv64, 0>;
def : ReadAdvance<ReadFSqrt32, 0>;
@ -238,9 +234,8 @@ def : WriteRes<WriteFCvtF16ToI32, []>;
def : WriteRes<WriteFDiv16, []>;
def : WriteRes<WriteFCmp16, []>;
def : WriteRes<WriteFLD16, []>;
def : WriteRes<WriteFMulAdd16, []>;
def : WriteRes<WriteFMA16, []>;
def : WriteRes<WriteFMinMax16, []>;
def : WriteRes<WriteFMulSub16, []>;
def : WriteRes<WriteFMul16, []>;
def : WriteRes<WriteFMovI16ToF16, []>;
def : WriteRes<WriteFMovF16ToI16, []>;
@ -260,9 +255,8 @@ def : ReadAdvance<ReadFCvtF16ToF32, 0>;
def : ReadAdvance<ReadFCvtF16ToI32, 0>;
def : ReadAdvance<ReadFDiv16, 0>;
def : ReadAdvance<ReadFCmp16, 0>;
def : ReadAdvance<ReadFMulAdd16, 0>;
def : ReadAdvance<ReadFMA16, 0>;
def : ReadAdvance<ReadFMinMax16, 0>;
def : ReadAdvance<ReadFMulSub16, 0>;
def : ReadAdvance<ReadFMul16, 0>;
def : ReadAdvance<ReadFMovI16ToF16, 0>;
def : ReadAdvance<ReadFMovF16ToI16, 0>;

18
llvm/lib/Target/RISCV/RISCVSchedule.td
View File

@ -42,14 +42,11 @@ def WriteFALU16 : SchedWrite; // FP 16-bit computation
def WriteFALU32 : SchedWrite; // FP 32-bit computation
def WriteFALU64 : SchedWrite; // FP 64-bit computation
def WriteFMul16 : SchedWrite; // 16-bit floating point multiply
def WriteFMulAdd16 : SchedWrite; // 16-bit floating point multiply add
def WriteFMulSub16 : SchedWrite; // 16-bit floating point multiply sub
def WriteFMA16 : SchedWrite; // 16-bit floating point fused multiply-add
def WriteFMul32 : SchedWrite; // 32-bit floating point multiply
def WriteFMulAdd32 : SchedWrite; // 32-bit floating point multiply add
def WriteFMulSub32 : SchedWrite; // 32-bit floating point multiply sub
def WriteFMA32 : SchedWrite; // 32-bit floating point fused multiply-add
def WriteFMul64 : SchedWrite; // 64-bit floating point multiply
def WriteFMulAdd64 : SchedWrite; // 64-bit floating point multiply add
def WriteFMulSub64 : SchedWrite; // 64-bit floating point multiply sub
def WriteFMA64 : SchedWrite; // 64-bit floating point fused multiply-add
def WriteFDiv16 : SchedWrite; // 16-bit floating point divide
def WriteFDiv32 : SchedWrite; // 32-bit floating point divide
def WriteFDiv64 : SchedWrite; // 64-bit floating point divide
@ -155,14 +152,11 @@ def ReadFALU16 : SchedRead; // FP 16-bit computation
def ReadFALU32 : SchedRead; // FP 32-bit computation
def ReadFALU64 : SchedRead; // FP 64-bit computation
def ReadFMul16 : SchedRead; // 16-bit floating point multiply
def ReadFMulAdd16 : SchedRead; // 16-bit floating point multiply add
def ReadFMulSub16 : SchedRead; // 16-bit floating point multiply sub
def ReadFMA16 : SchedRead; // 16-bit floating point fused multiply-add
def ReadFMul32 : SchedRead; // 32-bit floating point multiply
def ReadFMulAdd32 : SchedRead; // 32-bit floating point multiply add
def ReadFMulSub32 : SchedRead; // 32-bit floating point multiply sub
def ReadFMA32 : SchedRead; // 32-bit floating point fused multiply-add
def ReadFMul64 : SchedRead; // 64-bit floating point multiply
def ReadFMulAdd64 : SchedRead; // 64-bit floating point multiply add
def ReadFMulSub64 : SchedRead; // 64-bit floating point multiply sub
def ReadFMA64 : SchedRead; // 64-bit floating point fused multiply-add
def ReadFDiv16 : SchedRead; // 16-bit floating point divide
def ReadFDiv32 : SchedRead; // 32-bit floating point divide
def ReadFDiv64 : SchedRead; // 64-bit floating point divide