forked from OSchip/llvm-project
[InstCombine] Remove explicit check for impossible condition. Replace with assert
Summary: As far as I can tell the earlier call getLimitedValue will guaranteed ShiftAmt is saturated to BitWidth-1 preventing it from ever being equal or greater than BitWidth. At one point in the past the getLimitedValue call was only passed BitWidth not BitWidth - 1. This would have allowed the equality case to get here. And in fact this check was initially added as just BitWidth == ShiftAmt, but was changed shortly after to include > which should have never been possible. Reviewers: spatel, majnemer, davide Reviewed By: davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36123 llvm-svn: 309690
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llvm/lib/Transforms/InstCombine
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@ -534,7 +534,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
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// If the input sign bit is known to be zero, or if none of the top bits
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// are demanded, turn this into an unsigned shift right.
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if (BitWidth <= ShiftAmt || Known.Zero[BitWidth-ShiftAmt-1] ||
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assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
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if (Known.Zero[BitWidth-ShiftAmt-1] ||
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!DemandedMask.intersects(HighBits)) {
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BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
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I->getOperand(1));
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