forked from OSchip/llvm-project
[AMDGPU] gfx1010 changes for PAL metadata
Differential Revision: https://reviews.llvm.org/D61704 llvm-svn: 360353
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@ -252,12 +252,15 @@ static const char *getRegisterName(unsigned RegNum) {
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{PALMD::R_2CCA_SPI_SHADER_PGM_RSRC1_ES + 1, "SPI_SHADER_PGM_RSRC2_ES"},
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{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS, "SPI_SHADER_PGM_RSRC1_GS"},
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{PALMD::R_2C8A_SPI_SHADER_PGM_RSRC1_GS + 1, "SPI_SHADER_PGM_RSRC2_GS"},
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{PALMD::R_2E00_COMPUTE_DISPATCH_INITIATOR, "COMPUTE_DISPATCH_INITIATOR"},
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{PALMD::R_2E12_COMPUTE_PGM_RSRC1, "COMPUTE_PGM_RSRC1"},
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{PALMD::R_2E12_COMPUTE_PGM_RSRC1 + 1, "COMPUTE_PGM_RSRC2"},
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{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS, "SPI_SHADER_PGM_RSRC1_PS"},
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{PALMD::R_2C0A_SPI_SHADER_PGM_RSRC1_PS + 1, "SPI_SHADER_PGM_RSRC2_PS"},
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{PALMD::R_A1B3_SPI_PS_INPUT_ENA, "SPI_PS_INPUT_ENA"},
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{PALMD::R_A1B4_SPI_PS_INPUT_ADDR, "SPI_PS_INPUT_ADDR"},
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{PALMD::R_A1B6_SPI_PS_IN_CONTROL, "SPI_PS_IN_CONTROL"},
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{PALMD::R_A2D5_VGT_SHADER_STAGES_EN, "VGT_SHADER_STAGES_EN"},
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// Registers not known to code generation.
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{0x2c07, "SPI_SHADER_PGM_RSRC3_PS"},
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@ -283,7 +286,6 @@ static const char *getRegisterName(unsigned RegNum) {
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{0xa1c5, "SPI_SHADER_COL_FORMAT"},
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{0xa203, "DB_SHADER_CONTROL"},
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{0xa08f, "CB_SHADER_MASK"},
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{0xa1b6, "SPI_PS_IN_CONTROL"},
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{0xa191, "SPI_PS_INPUT_CNTL_0"},
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{0xa192, "SPI_PS_INPUT_CNTL_1"},
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{0xa193, "SPI_PS_INPUT_CNTL_2"},
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@ -334,7 +336,6 @@ static const char *getRegisterName(unsigned RegNum) {
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{0xa29b, "VGT_GS_OUT_PRIM_TYPE"},
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{0xa2ac, "VGT_GSVS_RING_ITEMSIZE"},
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{0xa2d5, "VGT_SHADER_STAGES_EN"},
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{0xa2ad, "VGT_REUSE_OFF"},
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{0xa1b8, "SPI_BARYC_CNTL"},
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