MIR Serialization: Serialize the 'undef' register machine operand flag.

llvm-svn: 241762

llvm/lib/CodeGen/MIRParser/MILexer.cpp

@@ -72,6 +72,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
       .Case("implicit-def", MIToken::kw_implicit_define)
       .Case("dead", MIToken::kw_dead)
       .Case("killed", MIToken::kw_killed)
+      .Case("undef", MIToken::kw_undef)
       .Default(MIToken::Identifier);
 }
 

llvm/lib/CodeGen/MIRParser/MILexer.h

@@ -41,6 +41,7 @@ struct MIToken {
     kw_implicit_define,
     kw_dead,
     kw_killed,
+    kw_undef,
 
     // Identifier tokens
     Identifier,
@@ -77,7 +78,7 @@ public:
 
   bool isRegisterFlag() const {
     return Kind == kw_implicit || Kind == kw_implicit_define ||
-           Kind == kw_dead || Kind == kw_killed;
+           Kind == kw_dead || Kind == kw_killed || Kind == kw_undef;
   }
 
   bool is(TokenKind K) const { return Kind == K; }

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -309,6 +309,9 @@ bool MIParser::parseRegisterFlag(unsigned &Flags) {
   case MIToken::kw_killed:
     Flags |= RegState::Kill;
     break;
+  case MIToken::kw_undef:
+    Flags |= RegState::Undef;
+    break;
   // TODO: report an error when we specify the same flag more than once.
   // TODO: parse the other register flags.
   default:
@@ -333,7 +336,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
   // TODO: Parse subregister.
   Dest = MachineOperand::CreateReg(
       Reg, Flags & RegState::Define, Flags & RegState::Implicit,
-      Flags & RegState::Kill, Flags & RegState::Dead);
+      Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef);
   return false;
 }
 
@@ -419,6 +422,7 @@ bool MIParser::parseMachineOperand(MachineOperand &Dest) {
   case MIToken::kw_implicit_define:
   case MIToken::kw_dead:
   case MIToken::kw_killed:
+  case MIToken::kw_undef:
   case MIToken::underscore:
   case MIToken::NamedRegister:
     return parseRegisterOperand(Dest);

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -220,6 +220,8 @@ void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
       OS << "dead ";
     if (Op.isKill())
       OS << "killed ";
+    if (Op.isUndef())
+      OS << "undef ";
     printReg(Op.getReg(), OS, TRI);
     // TODO: Print sub register.
     break;

llvm/test/CodeGen/MIR/X86/undef-register-flag.mir

@@ -0,0 +1,42 @@
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses the 'undef' register flags
+# correctly.
+
+--- |
+
+  define i32 @compute(i32 %a) #0 {
+  body:
+    %c = mul i32 %a, 11
+    ret i32 %c
+  }
+
+  define i32 @foo(i32 %a) #0 {
+  entry:
+    %b = call i32 @compute(i32 %a)
+    ret i32 %b
+  }
+
+  attributes #0 = { "no-frame-pointer-elim"="false" }
+
+...
+---
+name:            compute
+body:
+  - id:          0
+    name:        body
+    instructions:
+      - '%eax = IMUL32rri8 %edi, 11, implicit-def %eflags'
+      - 'RETQ %eax'
+...
+---
+name:            foo
+body:
+  - id:          0
+    name:        entry
+    instructions:
+      # CHECK: - 'PUSH64r undef %rax
+      - 'PUSH64r undef %rax, implicit-def %rsp, implicit %rsp'
+      - 'CALL64pcrel32 @compute, csr_64, implicit %rsp, implicit %edi, implicit-def %rsp, implicit-def %eax'
+      - '%rdx = POP64r implicit-def %rsp, implicit %rsp'
+      - 'RETQ %eax'
+...